Abstract
Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.
TopBackground
Field-Programmable Gate Arrays are silicon devices whose fabric hardware can be programmed to implement a particular digital system. The hardware programming capability of FPGAs gives them some advantages over Application Specific Integrated Circuits (ASIC) whose underlying fixed hardware is design to implement a specific digital system. Deploying and maintaining an FPGA-based system is faster and cheaper than implementing the same system in ASIC, since the ship is already made and just have to be configured to implement a specific function. Later, this function can be changed in the field without having to redesign a new chip and can even be reconfigured dynamically while running some other functionality. While is cheaper to design FPGA than an ASIC, the unit cost is higher for an FPGA. Therefore, the average cost of each of these devices depend on the production volume. The average unit cost of an ASIC decreases faster with the production volume than the cost of an FPGA unit. Therefore, there is a threshold from which ASICs are more cost effective.
The programming flexibility of FPGAs comes with a cost in terms of performance and power consumption. A large area of the FPGA (from 80 to 90%) is dedicated to routing and programming resources. It means that only 10-20% of the chip area is available to implement the hardware system. So, compared to an ASIC, a larger FPGA is necessary to implement the same functionality, the performance is worst due to the delay associated with the configurable routing and logic and the higher power consumption includes the power consumption of programming resources.
Any digital system consists of functional blocks, interconnections between these blocks and input/outputs connections between the functional blocks and off-chip circuits. An FPGA consists of programmable logic, interconnect and I/O modules that are tailored to implement a specific digital system.
Key Terms in this Chapter
Island-Style Routing: An interconnection architecture where routing organizes the FPGA as a two dimensional flat array surrounded by routing channels.
Fine-Grained Granularity: Refers to the granular size of the reconfigurable hardware at the bit level. Fine-grained granularity is typically associated to field-programmable gate arrays.
Reconfigurable Hardware: A hardware structure whose logic elements and their interconnections can be reconfigured to implement a particular logic circuit.
Look-Up Table (LUT): A small memory used to implement functions in an FPGA.
Coarse-Grained Granularity: Refers to the granular size of reconfigurable architectures consisting of arrays of units reconfigurable at the word level. A typical example is an arithmetic unit.
Digital Signal Processing Block (DSP): Configurable hard arithmetic blocks in FPGAs for arithmetic operations. DSPs can be interconnected to implement larger arithmetic operations.
Reconfigurable Computing (RC): A computing paradigm that uses reconfigurable hardware for computing purposes.
Block RAM (BRAM): A random access memory embedded in FPGAs for data storage. BRAMs can be interconnected to implement larger RAMs.
Granularity: Refers to the relative size of the reconfigurable elements in a reconfigurable hardware architecture.
Hierarchical Routing: An interconnection architecture where routing organizes the FPGA in clusters of logic blocks. Neighbor blocks are interconnected with local wires, while logic blocks in different clusters must go through one or more higher levels of routing.
Field-Programmable Gate Array (FPGA): An integrated circuit whose hardware can be configured after manufacturing.
Configurable Logic Block (CLB): The basic configurable logic resource of an FPGA. CLBs can be interconnected to implement complex logic functions.