A hardware immune system for the error detection of MC8051 IP core is designed in this chapter. The binary string to be detected by the hardware immune system is made from the concatenation of the PC values in two sequential machine cycles of the MC8051. When invalid PC transitions occurred in the MC8051, the alarm signal of the hardware immune system can be activated by the detector set. The hardware immune system designed in this chapter is implemented and tested on an FPGA development board, and the result is given in waveforms of the implemented circuits. The disadvantages and future works about the system are also discussed.
This section is organized as follows. Firstly, the Negative Selection Algorithm (NSA) by Forrest and her colleagues (Forrest et al., 1994) is briefly introduced, which is the fundamental algorithm applied in the hardware immune system. Secondly, a brief introduction to the architecture of the hardware immune system proposed by Bradley and Tyrrell (Bradley & Tyrrell, 2002b) is given. Related works about NSA and hardware immune systems are also given.
Key Terms in this Chapter
Hardware Immune System: Taking inspiration from the biological immune systems, a method of error detection for the sequential digital systems represented as finite state machines (FSM) is proposed by Bradley and Tyrrell as a novel approach to hardware fault tolerance. Negative Selection Algorithm (NSA) proposed by Forrest et al is applied to identify faults within a FSM by distinguishing invalid state transitions from valid state transitions. The state transitions of the system under monitoring are represented by binary strings in the form of “previous state / current state / current input”. In particular, it is shown that by use of partial matching in NSA, high fault coverage can be achieved with limited memory requirements. Bradley and Tyrrell also introduced a generic FSM immunization cycle that allows any system that can be represented as an FSM to be “immunized” against the occurrence of faulty operations.
Negative Selection Algorithm: In biological immune system, all new birth immature T-cells must undergo a process of negative selection in the thymus, where the self-reactive T-cells binding with self proteins are destroyed. When the mature T-cells are released to the blood circle, they can only bind with non-self antigens. Inspired by the self-nonself discrimination mechanism of the biological immune system, the Negative Selection Algorithm (NSA) is proposed by Forrest et al in 1994 as a change detection algorithm. The first step of the NSA is to collect a set of self strings that defines the normal state of the monitored system. Then the second step is to generate a set of detectors that only recognize non-self strings. Finally, the detector set is used to monitor the anomaly changes of the data to be protected.
MC8051 IP Core: MC8051 IP Core is a synthesizable VHDL microcontroller IP core provided by Oregano Systems – Design & Consulting GesmbH. It is binary compatible to the well known 8051 processor of Intel, and offers faster program execution compared to the original Intel 8051 devices since the processor’s architecture has been optimized. The VHDL source codes of the MC8051 IP Core are available for free under the GNU LGPL (Lesser General Public License). The source codes used in this chapter are downloaded from web page http://oregano.at/eng/8051.html.
Artificial Immune System: Inspired by several immunological principles, Artificial Immune Systems (AIS) emerged in the 1990s as a new branch of Computational Intelligence. Like artificial neural networks (ANNs), evolutionary algorithms (EAs), and cellular automata, AISs also try to extract ideas from the biological mechanisms in order to develop novel computational techniques for solving science and engineering problems. A number of AIS models are applied in areas like pattern recognition, fault detection, computer security, etc. Among various AIS models, negative selection, immune network and clonal selection are the most discussed models.
Finite State Machine: A model of computation consisting of a set of states, a start state, an input alphabet, and a transition function that maps input symbols and current states to a next state. Computation begins in the start state with an input string. It changes to new states depending on the transition function. There are many variants, for instance, machines having actions (outputs) associated with transitions (Mealy machine) or states (Moore machine), etc. (http://www.nist.gov/dads/HTML/finiteStateMachine.html). A finite state machine can be used both as a development tool for solving problems and as a formal way of describing specific device or program interactions.
Immunotronics: Immunotronics is a term combined from “immunological electronics”. It represents the immune-inspired hardware fault-tolerance technique proposed by Bradley and Tyrrell, i.e., the hardware immune system.
Error Detection: Discovering an error operation in hardware or software. In this chapter, the error detection indicates the detection of invalid state transitions occurred in the monitored system (the MC8051 IP Core) which can be represented as an FSM.