Synthetic Neuron Implementations

Synthetic Neuron Implementations

Snorre Aunet (University of Oslo, Norway & Centers for Neural Inspired Nano Architectures, Norway)
Copyright: © 2009 |Pages: 7
DOI: 10.4018/978-1-59904-849-9.ch228
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Many different synthetic neuron implementations exist, that include a variety of traits associated with biological neurons and our understanding of them. An important motivation behind the studies, modelling and implementations of different synthetic neurons, is that nature has provided the most efficient ways of doing important types of computations, that we are trying to mimick. Whether it is Artificial Neural Networks (ANNs) or other mixed signal systems, technology has always evolved in the direction of lower energy per unit computation ( Mead, 1990 ). Simple Neuron models as threshold elements, or perceptrons, are promising candidates for implementing future signal processing systems, including CMOS and SET ( Schmid & Leblebici, 2003 ), ( Beiu & Ibrahim, 2007 ). In this article a small number of published subthreshold, ultra low power, perceptrons / threshold elements are compared regarding power consumption, operational speed and defect tolerance. The “mirrored” gate operating in subthreshold and combined with redundancy, might be an interesting candidate for implementing artificial neural networks as well as other mixed-signal processing circuitry. Previously unpublished results demonstrate the mirrored gate producing appropriate binary outputs at 180 mV supply voltage, even when a transistor was cut off the supply voltage, for a redundancy factor of 2, using shorted outputs, as in ( Aunet & Hartmann, 2003 ).
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CMOS has been the dominant technology for implementing signal processing systems for decades, and will probably live alongside other nanotechnologies for a long time (ITRS, 2005). Due to needs for low power operation for about any future signal processing technology and that CMOS and similar technologies probably will be mainstream for the foreseeable future, the scope of this paper is limited to simple CMOS, ultra low power circuit topologies. Subthreshold circuits (Swansson & Meindl, 1972), using a supply voltage below the inherent threshold voltage of the transistors, consume less power than other low power circuits (Soeleman, Roy & Paul, 2001). Therefore we look at subthreshold neuron (“perceptron”) implementations in this paper, and concentrate on different metrics including circuit complexity, operational speed, power consumption and defect tolerance.

Reducing the power supply voltage through using ever more modern CMOS technologies and subthreshold operation reduces the number of inputs one could use for the threshold elements, depicted in Figure 1 (Aunet, 2002). Also, since only 2 inputs is optimal to implement any arbitrary neural network (Beiu & Makaruk, 1998) we have restricted the treatment to basic building blocks having a maximum fan-in of 3.

Figure 1.

The binary output, Y, depends on if the weighted sum of inputs X1, X2,…,Xn exceeds a certain Threshold, T.

The first simple mathematical model of the biological neurons, published by McCulloch and Pitts in 1943, calculates the sign of the weigthed sum of inputs. Sometimes such circuits are called threshold logic gates or threshold elements, illustrated in Figure 1. Such perceptrons may be used to implement Neural Networks as well as digital signal processing. For a review on a wide range of VLSI implementations the reader might confer (Beiu, Avedillo & Quintana, 2003).


Ultra Low Power Neurons, Speed And Reliability

The main focus is on different subthreshold ultra low power perceptrons and how they compare regarding power consumption, operational speed and reliability.

Key Terms in this Chapter

Mismatch: Ideally identically constructed elements on an integrated circuits have a mismatch when they differ in their physical properties after production of the chip.

Minority-3 Gate: A minority 3 gate outputs a logic “0” signal if, and only if, 2 or 3 out of it’s three binary inputs are “1”.

Parameter Variations: Parameters describing physical traits of integrated circuits may have variations due to mismatch, for example the threshold voltages of transistors.

Full Adder: Circuit that produces the binary sum and carry when adding two binary numbers.

Yield: In this paper the term yield refers to the ratio of functional circuits to the total number of simulated circuits. Often yield refers to the ratio of functional chips to the total number of manufactured chips.

Neuron: Electrically excitable cells in the nervous system that process and transmit information.

SET: Single Electron Transistor.

Monte Carlo Simulations: Computer simulations basing the results on statistical distribution of parameters.

Nanoscale CMOS: CMOS technologies where dimensions smaller than 100 nm is critical to the functioning of the produced chip.

Perceptron: Type of artificial (feedforward) Neural Network.

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