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What is Formal Model

Handbook of Research on Embedded Systems Design
A model which description is complete and non-ambiguous.
Published in Chapter:
Industrial Experiments in IMS, ATC, and SDR Projects of Property Verification Techniques
Emmanuel Gaudin (PragmaDev, France)
Copyright: © 2014 |Pages: 14
DOI: 10.4018/978-1-4666-6194-3.ch019
Abstract
The increasing complexity of embedded systems calls for verification techniques to make sure the systems behave properly. When it comes to safety-critical systems, this aspect is even more relevant and is now taken into consideration by certification authorities. For that matter, property verification is accepted to be done not only on the system itself but also on a representative model of the system. This chapter first introduces the different properties and how they could be expressed. Then associated modeling languages characteristics are discussed to describe the systems on which the properties can be verified. Finally, different technologies to verify the properties are presented, including some practical examples and existing tools. This last part is illustrated by several research projects such as the PRESTO ARTEMIS European project and the exoTICus System@tic Paris Region competitiveness cluster project.
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More Results
Formal Analysis of Workflows in Software Development
Any model with well-formed syntax and semantics, such that it is amenable to systematic (usually automatable) processing and analysis subject to logical rules.
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Location-Awareness with Action Systems
Model based on rigorous methods and formats; it often enables analysis to be performed on the models.
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