What is Hardware Immune System

Taking inspiration from the biological immune systems, a method of error detection for the sequential digital systems represented as finite state machines (FSM) is proposed by Bradley and Tyrrell as a novel approach to hardware fault tolerance. Negative Selection Algorithm (NSA) proposed by Forrest et al is applied to identify faults within a FSM by distinguishing invalid state transitions from valid state transitions. The state transitions of the system under monitoring are represented by binary strings in the form of “previous state / current state / current input”. In particular, it is shown that by use of partial matching in NSA, high fault coverage can be achieved with limited memory requirements. Bradley and Tyrrell also introduced a generic FSM immunization cycle that allows any system that can be represented as an FSM to be “immunized” against the occurrence of faulty operations.

A Hardware Immune System for MC8051 IP Core

Xin Wang (University of Science and Technology of China, China), Wenjian Luo (University of Science and Technology of China, China), Zhifang Li (University of Science and Technology of China, China), and Xufa Wang (University of Science and Technology of China, China)