A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC

A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC

K. Tatas (Department of Computer Science and Engineering, Frederick University, Nicosia, Cyprus), K. Siozios (School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece), A. Bartzas (School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece), C. Kyriacou (Department of Computer Science and Engineering, Frederick University, Nicosia, Cyprus) and D. Soudris (School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece)
DOI: 10.4018/jaras.2013070101
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Abstract

This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.
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Previous Work

A number of NoC architectures have been implemented and evaluated in both FPGA and ASIC platforms, among them (Ehliar & Liu, 2007; Genko, Atienza, & De Micheli, 2005). Furthermore, frameworks and tools for high-level exploration for NoC architectures exist (Kumar, Hansson, Huisken, & Corporaal, 2007).

In Leary and Chatha (2010) a holistic algorithm for NoC synthesis able to address all these requirements together in an integrated manner was presented. However, the synthesis methodology provided does not provide Register Transfer-Level descriptions that can readily be used for system implementation.

In Strano, A., Bertozzi, D., Angiolini, F., Di Gregorio, L., Sem-Jacobsen, F. O., Todorov, V., Flich, J., Silla, F., & Bjerregaard, T. (2012) a more complete framework for the design of NoC is presented, but it does not include FPGA rapid prototyping.

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