A Parallel Software Architecture for the LTE Protocol on a Multi-Core Mobile Modem

A Parallel Software Architecture for the LTE Protocol on a Multi-Core Mobile Modem

Anas Showk (KROHNE Innovation GmbH, Duisburg, Germany) and Attila Bilgic (KROHNE Messtechnik GmbH, Duisburg, Germany)
DOI: 10.4018/ijertcs.2013070102
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Coming wireless communication standards like Long Term Evolution (LTE) promise to bring a drastic increase in data rate for the end user. To facilitate this evolution, sophisticated technology for the mobile equipment is required. Most research focuses on the signal processing in the physical layer whereas the computational capabilities for protocol processing are neglected. This paper describes novel software architecture and load balancing for the LTE protocol stack that allows concurrent execution on a multi-core processor and thus allows for exploiting all the advantages like higher performance through parallelism at low power consumption. The layered protocol is developed using Specification and Description Language (SDL). In addition, the LTE protocol stack is parallelized and executed on a multi-core processor, by employing the SDL processes concurrency. Moreover, the LTE system is scheduled on multi-core by customizing the SDL scheduler to implement a data pipeline scheduler. Furthermore, a new load balancer scheme is proposed by moving the load balancer to the modem subsystem’s layer and using the SDL process migration concept. The performance of the LTE protocol implementation using the new scheme beats the classic thread migration scheme by more than 50% on single as well as multi-core platforms. The data throughput using the new scheme increases on two, three, or four cores, compared to single core, by about 195%, 290%, and 360%, respectively, and thus shows an excellent scalability for up to three cores and still giving reasonably good results for four cores.
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1. Introduction

The Long Term Evolution (LTE) standard is the progression of the Global System for Mobile Communications (GSM) and Universal Mobile Telecommunications System (UMTS) standards. The standardization process for LTE is introduced by the Third Generation Partnership Project (3GPP) in release 8. The 3GPP work on LTE has been going on since 2004 and is finalized by the end of 2008. The LTE standard is designed to enable a data rate of 100 Mbit/s in the downlink and of 50 Mbit/s in the uplink direction (3rd Generation Partnership Project (3GPP), 2011). Furthermore, the LTE standard category 5 design target is to achieve 300 Mbit/s data rate using the Multiple Input Multiple Output (MIMO) technique (Robson, 2009). Therefore, supporting high data rates while minimizing power is the key design challenge for LTE. The functionality of a mobile handset can basically be divided into three categories, the baseband processing for the PHYsical layer (PHY), modem functionalities (for packet processing in the upper layers of wireless protocols), in addition to the application tasks as shown in Figure 1. While the baseband processing is usually implemented in hardware, the modem and the application subsystems have inherently different requirements on the computational system they use to fulfill their tasks. Whereas the modem functionality is determined by soft real-time operation, the application domain requires high flexibility and extensibility. Today’s approach either combines the two on one core processor or separates the domains physically on two or more cores with weak interactions as illustrated by Figure 1, which is very inflexible and provides little scalability (eMuCo Project Consortium, 2008).

Figure 1.

The classical smart phone platform shows week interaction between subsystems

To provide a hardware platform for LTE terminals with satisfactory performance, the classical option is to increase the clock frequency of the modem subsystem’s single-core processor, which increases power consumption dramatically. The computational capabilities provided by single-core processors, at reasonable power consumption, is hardly enough for the LTE protocol stack processing demands (Szczesny et al., 2009, 2010). The other option is the use of multiple processing cores as depicted in Figure 2 to offer a high computational capability at reasonable power consumption, which makes multi-core processors the favorable candidate for future mobile terminals. In addition, the contradiction of exponentially increasing computational performance requirements and low power consumption in combination with high flexibility can be solved by a multi-core approach. Moreover, multi-core increases the dimensions for resource allocation and scalability. However, in this article we concentrate on modem subsystem software in order to provide a parallel software architecture for efficient execution on multi-core hardware platforms.

Figure 2.

The LTE mobile terminal architecture utilizes a multi-core hardware platform

The multi-core performance scalability and gain heavily depend on the executed software algorithms and their implementations. However, in most cases, algorithms are not easily parallelizable, thus software developers need to spend much effort in customizing the algorithm to build parallel software architecture. According to Amdahl’s law, the maximum speedup of a multi-core system depends not only on the number of active cores but also on the fraction of the software that can be executed in parallel (Herlihy & Shavit, 2008). Accordingly, the parallelization of software is currently a hot research topic (Sriram & Bhattacharyya, 2009).

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