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Top1. Introduction
The Long Term Evolution (LTE) standard is the progression of the Global System for Mobile Communications (GSM) and Universal Mobile Telecommunications System (UMTS) standards. The standardization process for LTE is introduced by the Third Generation Partnership Project (3GPP) in release 8. The 3GPP work on LTE has been going on since 2004 and is finalized by the end of 2008. The LTE standard is designed to enable a data rate of 100 Mbit/s in the downlink and of 50 Mbit/s in the uplink direction (3rd Generation Partnership Project (3GPP), 2011). Furthermore, the LTE standard category 5 design target is to achieve 300 Mbit/s data rate using the Multiple Input Multiple Output (MIMO) technique (Robson, 2009). Therefore, supporting high data rates while minimizing power is the key design challenge for LTE. The functionality of a mobile handset can basically be divided into three categories, the baseband processing for the PHYsical layer (PHY), modem functionalities (for packet processing in the upper layers of wireless protocols), in addition to the application tasks as shown in Figure 1. While the baseband processing is usually implemented in hardware, the modem and the application subsystems have inherently different requirements on the computational system they use to fulfill their tasks. Whereas the modem functionality is determined by soft real-time operation, the application domain requires high flexibility and extensibility. Today’s approach either combines the two on one core processor or separates the domains physically on two or more cores with weak interactions as illustrated by Figure 1, which is very inflexible and provides little scalability (eMuCo Project Consortium, 2008).
Figure 1. The classical smart phone platform shows week interaction between subsystems
To provide a hardware platform for LTE terminals with satisfactory performance, the classical option is to increase the clock frequency of the modem subsystem’s single-core processor, which increases power consumption dramatically. The computational capabilities provided by single-core processors, at reasonable power consumption, is hardly enough for the LTE protocol stack processing demands (Szczesny et al., 2009, 2010). The other option is the use of multiple processing cores as depicted in Figure 2 to offer a high computational capability at reasonable power consumption, which makes multi-core processors the favorable candidate for future mobile terminals. In addition, the contradiction of exponentially increasing computational performance requirements and low power consumption in combination with high flexibility can be solved by a multi-core approach. Moreover, multi-core increases the dimensions for resource allocation and scalability. However, in this article we concentrate on modem subsystem software in order to provide a parallel software architecture for efficient execution on multi-core hardware platforms.
Figure 2. The LTE mobile terminal architecture utilizes a multi-core hardware platform
The multi-core performance scalability and gain heavily depend on the executed software algorithms and their implementations. However, in most cases, algorithms are not easily parallelizable, thus software developers need to spend much effort in customizing the algorithm to build parallel software architecture. According to Amdahl’s law, the maximum speedup of a multi-core system depends not only on the number of active cores but also on the fraction of the software that can be executed in parallel (Herlihy & Shavit, 2008). Accordingly, the parallelization of software is currently a hot research topic (Sriram & Bhattacharyya, 2009).