An Improved Unified AES Implementation Using FPGA

Introduction

Today the world has entered into the 5G communication with high-speed data transmission in real-time. The high-speed data transfer and higher connectivity increase the susceptibility for stealing information. The devices are becoming smart day by day with technological advancement. These intelligent devices and systems require fast and secure end-to-end communication with a large size of information in a real-time environment (Dong et al., 2019). The multiple connectivity in smart devices cause more susceptibility to the information theft. Such a concern can be addressed using encryption of the electronic information before the transmission.

Cryptography ensures data secrecy and integrity by altering information. Cryptography has a long back history that uses mathematical approaches and some rules called an algorithm. Cryptography has features of confidentiality, integrity, and authentication. Generally, cryptography is classified into three types- Symmetric key, Asymmetric key, and HASH function. Symmetric and Asymmetric cryptography utilizes a key, but the HASH function does not require any key. Symmetric key cryptography is very fast and simple. Therefore, it is widely used in the world. DES (Data Encryption Standard) was famous for cryptography till the last decade. A new encryption algorithm, AES, is widely accepted globally (Elbirt et al., 2001).

The Rijndael algorithm was selected for the Advanced Encryption Standard (AES) algorithm, and the National Institute of Standard and Technology (NIST) approved the AES encryption in 2001. The AES cipher has three variants of 128-bit, 192-bit, 256-bit key with 128-bit data, and AES process the data as four groups of 4 bytes. It has 10, 12, and 14 rounds with a key size of 128-bit, 192-bit, and 256-bit, respectively. The AES contains ten rounds of transformations. Each round has four identical transformations; Substitution byte, Shift Row, Mix Column, and Add Round Key. Add Round block performs XOR operation. All operations can be combined into XOR operations and table lookups. The Substitution byte and Key expansion block play a significant role in confusion development in the encryption process. Hardware-supported implementation of the AES algorithm is more secure, faster, and consumes less power than its software-based implementation. Still, the recent cryptography applications are implemented on FPGAs either with pipelined architecture or low power and low-cost architecture (Jun et al., 2010). FPGAs are getting most popular for designers because of their reconfigurable nature and fast implementation. FPGAs are reprogrammable in hardware as well as software design implementation. FPGA has significantly higher degrees of flexibility. The modern FPGAs have six inputs LUT, and they are utilized in complex design implementation. Researchers have developed many designs with algorithm for the area, delay, and power optimization. They have implemented their design with AES encryption with FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) design.

This proposed work has designed AES core, consisting of encryption and decryption having a shared secret key. This core is designed in such a way that information can be shared efficiently and securely in duplex mode. Simulation, synthesis, and implementation have been performed in Xilinx ISE software using Verilog HDL (Hardware Descriptive Language) code. Synthesis has been performed on Virtex-7 FPGA platform. The performance measures are resource utilization, clock speed, and throughput. The synthesized data have been compared with existing works in a unified AES core.

The main contributions are as follows:

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  A unified AES core has been proposed in this article, and Mix column operations are optimized in this design as they alter the information in just a vertical manner, and the same thing happens in other operations of AES. This design has fewer mix column operations than traditional AES.

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  Our design has been successfully implemented on the FPGA platform and verified for its functionality.

The rest of the paper is organized as follows. The background study and related work of AES have been presented in the next section. The operations and the explanation of each process have been explained in section 3. The proposed method has been described in section 4. The simulated output and synthesized output have been discussed with previous literature in section 5. Finally, the conclusion is drawn in section 6.