Analysis of Direct Sensor-to-Embedded Systems Interfacing: A Comparison of Targets’ Performance

Analysis of Direct Sensor-to-Embedded Systems Interfacing: A Comparison of Targets’ Performance

Lars E. Bengtsson (University of Gothenburg, Sweden)
Copyright: © 2012 |Pages: 16
DOI: 10.4018/ijimr.2012010103


This paper is concerned with the direct interfacing of resistive sensors to different embedded targets. The author uses the idea of “direct sensor-to-microcontroller” technique where analog sensors are interfaced directly to inherently digital controllers and we compare the performance of this technique when applied to a typical microcontroller (PIC18), a CPLD and an FPGA. Experimental results show that 5 V systems, like the PIC18 controller, have an advantage over 3.3 V systems in terms of better precision performance, while the CPLD outperforms both the microcontroller and the FPGA in terms of accuracy. The accuracy depends mainly on the output impedance of the system’s I/O ports and the precision depends mainly on trigger level noise. The PIC18 controller also has the best performance in terms of linearity and sensitivity. A lot of works have been published concerning direct interfacing to microcontrollers, but little attention has been paid to alternative targets like CPLD and FPGA. This work will benchmark these different kinds of targets and prove that the direct interfacing technique can also be applied to CPLDs and FPGAs.
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Traditionally, analog sensors are interfaced to embedded systems via a combination of signal conditioning electronics and an analog-to-digital converter (ADC). Typically, some, or all, of the signal conditioning electronics is integrated in the sensor circuit and the ADC is typically integrated in the embedded controller. Figure 1 illustrates a typical distribution of components between the “sensor” circuit and the “system” circuit.

Figure 1.

Traditional data acquisition system

During the last decade, there’s been a trend towards interfacing sensors directly to microcontrollers, without the use of ADCs (Cox, 1997; Merritt, 1999; Custodio et al., 2001; Jordana et al., 2003; Reverter et al., 2005; Lepowski, 2004; Reverter & Pallàs-Areny, 2006). The major advantage is that this reduces the overall cost of the acquisition system. The main idea is to transfer the analog signal variation caused by the sensor, into a quasi digital signal that can be measured by one of the controller’s embedded timers. A variation in an analog voltage is transferred into an analog variation in either frequency, time duration or duty cycle (“quasi digital”) as illustrated in Figure 2 (Reverter & Pallàs-Areny, 2005; Viorel, 2006).

Figure 2.

Analog signals are transferred into quasi digital signals

Quasi digital signals are easily measured by any embedded system with a standard timer; measuring analog variations in time is easier (and more cost efficient) than measuring variations in an analog voltage. Also, performance parameters like dynamic range and noise immunity, typically improve when you measure a variation in time instead of a variation in analog voltage (Pallàs-Areny & Webster, 2001).

Exactly how this direct sensor interfacing is implemented depends on the sensor, whether it is resistive, capacitive or part of a Wheatstone bridge or not. We treat only resistive sensors (not being part of a bridge circuit) here. This includes, for example, common RTDs (Resistive Thermal Devices) like the Pt-1000 sensor.

Figure 3 illustrates the basic idea of how a resistive sensor is interfaced directly to a controller.

Figure 3.

Direct interfacing of resistive sensor

During the first stage, I/O pin 2 is configured as output and set high while I/O pin 1 is configured as input (high impedance). I/O pin 2 will charge the capacitor to VOH (I/O pin output high level). During the second stage, the pins are reconfigured; pin 2 becomes high impedance and pin 1 is configured as an output pin and set low. Hence the capacitor will discharge through the sensing element’s resistance RS. The discharging continues until the voltage on pin 2 reaches the threshold level for input logic low (VIL). Figure 4 shows the charge/discharge timing diagram on I/O pin 2.

Figure 4.

Charging/Discharging at I/O-pin 2

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