Analytical Model for High–Level Area Estimation of FPGA Design

Analytical Model for High–Level Area Estimation of FPGA Design

Rachna Singh (BCE, Bhopal, India) and Arvind Rajawat (MANIT, Bhopal, India)
DOI: 10.4018/IJERTCS.2016070103
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Abstract

FPGAs have been used as a target platform because they have increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercially affordable. These trends make FPGAs an alternative in application areas where extensive data processing plays an important role. Consequently, the desire emerges for early performance estimation in order to quantify the FPGA approach. A mathematical model has been presented that estimates the maximum number of LUTs consumed by the hardware synthesized for different FPGAs using LLVM.. The motivation behind this research work is to design an area modeling approach for FPGA based implementation at an early stage of design. The equation based area estimation model permits immediate and accurate estimation of resources. Two important criteria used to judge the quality of the results were estimation accuracy and runtime. Experimental results show that estimation error is in the range of 1.33% to 7.26% for Spartan 3E, 1.6% to 5.63% for Virtex-2pro and 2.3% to 6.02% for Virtex-5.
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The most important challenge in the embedded system design is HW/SW partitioning. Finding an optimal partition is hard because of the large number and different characteristics of the components that have to be considered. For the Hardware implementation, the most important characteristics to be considered are: hardware area, delay, latency, and power consumption. A quick and accurate estimation of such characteristics is of a paramount importance to guide the decision making process. An excellent survey of the hardware characteristics estimation techniques is presented in (González & Sánchez, 2011).

Several approaches for estimating area and performance parameters of FPGA designs have been proposed. The methodology proposed in (Niu & Zhang, 2013) estimates area and timing based on models of the mapping process. Starting with a register transfer level (RTL) description, the area is estimated by predicting look-up table (LUT) mapping, configurable logic block (CLB) construction, and placement. The subsequent timing estimation is based on predicting CLB delay, wiring delay, and input-to-output delay. This approach is strongly integrated into the design flow since the placement information of the area estimation has to be taken into account by the placement tool.

Area estimation for different input description languages is widely studied like C (Kunz & Zipf, 2012; Niu & Zhang, 2013; Eerola & Nurmi, 2014), SA-C (Rao & Grout, 2015), SystemC (Silveira & Costa, 2015), MATLAB (Schumacher & Jha, 2008), Simulink (Reyneri & Lavagno, 2001). Most of the published work performs a transformation step to express the input description into an Intermediate Representation (IR) such as Trimaran IR (Niu & Zhang, 2013), Control Data Flow Graph (CDFG) (Abdelhalim & Habib, 2008) and then, apply the estimation process on the intermediate format. Most of the techniques detect the resource sharing opportunities through scheduling (Milder & P¨uschel, 2006), according to the complexity of the design (Kulkarni & Kurdahi, 2006), or by using a derived resource utilization formula (Rao & Grout, 2015).

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