Analyze Physical Design Process Using Big Data Tool: Hidden Patterns, Performance Measures, Predictive Analysis and Classifying Logs

Analyze Physical Design Process Using Big Data Tool: Hidden Patterns, Performance Measures, Predictive Analysis and Classifying Logs

Waseem Ahmed (Department of Computer Science, University of Regina, Regina, Canada) and Lisa Fan (Department of Computer Science, University of Regina, Regina, Canada)
DOI: 10.4018/IJSSCI.2015040102


Physical Design (PD) Data tool is designed mainly to help ASIC design engineers in achieving chip design process quality, optimization and performance measures. The tool uses data mining techniques to handle the existing unstructured data repository. It extracts the relevant data and loads it into a well-structured database. Data archive mechanism is enabled that initially creates and then keeps updating an archive repository on a daily basis. The logs information provide to PD tool is a completely unstructured format which parse by regular expression (regex) based data extraction methodology. It converts the input data into the structured tables. This undergoes the data cleansing process before being fed into the operational DB. PD tool also ensures data integrity and data validity. It helps the design engineers to compare, correlate and inter-relate the results of their existing work with the ones done in the past which gives them a clear picture of the progress made and deviations that occurred. Data analysis can be done using various features offered by the tool such as graphical and statistical representation.
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1. Introduction

The PD tool details about creation of a single point solution for data gathering, data structuring, error checking and report generation for IC chip production and design. The solution once created is being used as the benchmark for quality tracking and model estimation as the test data from all the chips at the moment of designing, when fed to the proposed solution, aims to generate a successful report without any error. The proposed solution is a great technological leap for the physical design engineers as they no longer have to manually check the test logs from several data servers. Previously, there was no solution available to accomplish this task as the data to be tested was in a raw and poorly structured form.

The solution is designed as an ETL (extract, transform and load) architectural design pattern based solution. It performs the tasks needed for data extraction from the unstructured data source followed by data cleansing, data transforming and finally data staging which provides a well-structured dataset to the solution's database. The front-end module is designed to support user-data controlling, data validation, data visualization and report generation.

The project's ecosystem is entirely based on physical design process in ASIC world. The design engineers works on designing cutting-edge chips. A chip consists of subchips each responsible for a specific functionality. Each of these subchips comprises of numerous floorplan blocks. The design engineers are responsible to build logic model as well as verify each (floorplan) block. They analyze parameters of the chip like the placement of blocks (number of devices known as flopcounts, number of clocks) and standard cell area, metal pins, clock and closure timing, measure clock latency and skewness, layout versus schematic, design rule check, electrical rule check and so on. Initially, PD tool focus is on Primetime corners such as I/O- setup/hold time, Core setup/hold time, Design Rule Checking ICV’s, ICC, Layout Versus Schematic (LVS), Primetime Electric Rule Check (ERC). At the end, the PD engineers tapeout design and store values in log files (unstructured data repository). This log file data is updated by synchronically at design, compile and test logics. Then, PD tool gather and analyze log data at central database and PD tool is contributing greatly to optimize their chip’s design and process.

Furthermore, we conducted experiment on sixteen datasets fetched from PD tool database and classified them using three classification algorithms i.e. Naïve Bayes, Decision Tree, and Multilayer Perceptrons. In this paper, datasets from PD database at four subchip levels were extracted and every subchip had four types of information which means 4 (subchips) x 4 (types) equal to sixteen datasets. Finally, appropriate classification algorithm by comparing their accuracy and precision gets selected.

Although several studies have been conducted on comparing classification algorithm’s performance on different types of datasets, very few have focused on same type of datasets. However, the most extensive work was carried out on numerous datasets in STATLOG project (1995) by King, Feng and Sutherland. They argued on interpretation results, the variation in the data and the algorithm used in different type of datasets. In 1997 Hand and Henley conducted an experiment of different statistical classification approaches used for credit rating datasets. Berardi, Patuwo and Hu presented a principle approach for building and evaluating neural networks models for e-commerce datasets which’s done in 2004. And also, Classification algorithms have been used in the medical field. For example, Eftekhar et al. (2005) compared the performance of artificial neural network and multivariable logistic regression models in prediction of outcomes of head trauma. In 2002, J. Eng has done experiment of neural network with one hidden layer and multivariate logistic regression on pulmonary embolism datasets. The objective of the above discussion is to show the work that has been done on multiple datasets with different domains. But our concentration of work is on multiple datasets with unique domain. Moreover, we choose physical design process from ASIC world; extract the historical model data from LOG files; push data to structure database; classify data values based on industry engineer’s definition and conduct experiment using three classification algorithms to support their definition. It can help engineer to select the best definition for chip design and can be used to tape-out design efficiently.

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