Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm

Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm

Pankaj P. Prajapati (Gujarat Technological University, L. D. College of Engineering, Ahmedabad, India) and Mihir V. Shah (Gujarat Technological University, L. D. College of Engineering, Ahmedabad, India)
Copyright: © 2020 |Pages: 9
DOI: 10.4018/IJAMC.2020010103


The circuit design of the CMOS based analog part of a mixed-signal integrated circuit (IC) needs a large fraction of the overall design cycle time. The automatic design of an analog circuit is inevitable, seeing recently development of System-on-Chip (SOC) design. This brings about the need to develop computer aided design (CAD) tools for automatic design of CMOS based analog circuits. In this article, a Cuckoo Search (CS) algorithm is presented for automatic design of a CMOS Miller Operational Transconductance Amplifier (OTA). The source code of the CS algorithm is developed using the C language. The Ngspice circuit simulator has been used as a fitness function creator and evaluator. A script file is written to provide an interface between the CS algorithm and the Ngspice simulator. BSIM3v3 MOSFET models with 0.18 µm and 0.35 µm CMOS technology have been used to simulate this circuit. The simulation results of this work are presented and compared with previous works reported in the literature. The experimental simulation results obtained by the CS algorithm satisfy all desired specifications for this circuit.
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The circuit design of CMOS based analog and the mixed-signal system is an eminent area for developing technical and commercial significance (Kammara, Palanichamy, & König, 2016). There are many optimization methods presented earlier and in current time for automatic synthesis of analog circuits. A lot of research work has been devoted to evolutionary algorithm-based optimization of fundamental CMOS based analog circuits such as differential amplifier, operational amplifier (op-amp), and operational transconductance amplifier (OTA). These circuits are used as the main heart of many interface circuits, like analog to digital converters (ADC), digital to analog converters, filters, and comparators. So an optimum design of fundamental CMOS based analog circuits is the basis of a design background for various applications. The main evolutionary algorithms (EA) are particle swarm optimization (PSO) (Kennedy and Eberhart, 1995) Genetic algorithm (GA) (Kruiskamp, 1995), differential evolution (DE) (Stron and Price, 1997), harmony search (HS) (Geem, Kim, & Loganathan, 2001), ant colony optimization (ACO) (Dorigo, Maniezzo, & Golomi, 1996), and artificial bee colony optimization (ABC) (Karaboga, 2005) become common in engineering applications and other fields. These algorithms have also been used to a lesser degree for optimization of CMOS based analog circuits. In (Ferreira, Tales, & Robson, 2007), an ultra-low-voltage ultra-low-power CMOS Miller OTA with rail-to-rail input/output swing was designed in 0.35µm CMOS technology. In (Dammak, Bensalem, Zouari, & Loulo, 2008), gm/ID methodology was presented for folded cascode OTA design in 0.35µm CMOS technology. An ultra-low power CMOS Miller OTA and a three-stage CMOS Miller op-amp were optimized by GA, PSO, and HPSO in (Thakker, Baghini, & Patil, 2009) and the authors concluded that HPSO converges better than the other algorithms. Some important works are reported in (Sabat, Kumar, & Udgata, 2009) (Vural & Ayten, 2012) (Kudikala, Sabat, & Udgata, 2011). DE, PSO and ABC algorithms were used to optimize CMOS Miller OTA in (Sabat, Kumar, & Udgata, 2009) and authors concluded that DE achieves good performance than PSO, whereas ABC does not touch the goals. ABC, DE, HS, and PSO algorithms were used to optimize nth order filters in (Vural & Ayten, 2012) and the authors concluded that HS is the fastest procedures but has the maximum fault while the other procedures converged superior. The performance of HS and DE algorithms were compared in (Kudikala, Sabat, & Udgata, 2011) and the authors have also derived the same conclusion. Two-stage CMOS op-amp was designed using 0.18 μm and 0.35 µm CMOS process technology in (Prajapati & Shah, 2015). HS, standard PSO (SPSO) 1995, and SPSO 2007 were compared in (Kammara, Palanichamy, & König, 2016) and the authors concluded that SPSO95 and HS deliver fast solutions getting preferred target values. DE algorithm has been used to optimize various analog circuits like CMOS voltage divider, CMOS common source amplifier, CMOS three stage current starved voltage-controlled oscillator and CMOS differential amplifier with current mirror load using 180 nm CMOS technology in (Sharma & Prajapati, 2016). The performance of the modified PSO algorithm with standard PSO and ABC algorithms had been compared by optimizing bulk driven OTA and two-stage CMOS op-amp using 130 nm CMOS technology in (Patel & Thakkar, 2016). In (Akbari, Shokouhifar, Hashemipour et al., 2016), optimization of OTAs with power consumption minimization and noise optimization using ACO was presented. PSO based methodology has been tested to size rail to rail CMOS Miller OTA using 0.35 µm and 0.18 µm standard CMOS technology parameters in (Prajapati & Shah, 2017).

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