Automatic Machine Code Generation for a Transport Triggered Architecture using Cartesian Genetic Programming

Transport Triggered Architecture

The transport triggered architecture (TTA) was created in the 1980's, as a development of the Very Long Instruction Word (VLIW) architecture (Corporaal, 1998). The TTA usually contains an instruction decoder, an interconnection network and a number of functional units (FU), as shown in Figure 1. Functional units and the decoder are connected through data and address buses. A single data/address bus pair is called a slot. A processor can have multiple slots to allow parallelism. An input/output interface of a functional unit is called a port. Ports are usually globally addressable. The connection of a port to a slot is called a socket and the number of conjunctions in a socket is flexible.

Figure 1.

Transport triggered architecture (Mudry, 2009)