On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

Introduction

High-speed serial point to point connections are proven to be energy and area efficient solutions for on-chip data transmissions over long distances in the range of some mm in networks-on-chip (NoCs) (Mensink et al., 2010; Walter et al., 2012). Although conventional 2D-mesh NoC topologies require only shorter point to-point links between adjacent cores, the proposed long distance interconnects can enable efficient implementation of advanced NoC topologies like for example hierarchical 2D-mesh NoCs (Winter et al., 2010), where higher layer point-to-point links bridge distances over multiple cores. As link data rates increase, the influence of process variations gets more severe especially in sub-100nm CMOS technologies. To achieve high data rates and maximize yield, calibration techniques have to be employed to compensate static mismatch variations. In Höppner et al. (2010) a calibration strategy with optimal sizing of compensation delay elements has been proposed. However, measurement access to on-chip signal characteristics is required. Asynchronous sub-sampling, where a high-speed signal is periodically sampled by a low-speed clock, is widely used for on-chip measurement purposes. In Schaub et al. (2008) on-chip oscilloscopes using asynchronous sampling clocks are presented which allow measurement of high-speed signals but require low jitter sampling clocks. This is a major drawback for complex MPSoCs where measurement signals have to be distributed over longer distances with negligible circuit and area overhead. In Amrutur et al. (2010) measurement of static skews of periodic signals is proposed using statistical averaging. This approach eases integration due to relaxed requirements for sample clock quality. Using this method periodic on-chip signals whose period is in the range of sample clock jitter can be characterized.

This work presents an asynchronous sub-sampling technique (Höppner et al., 2011) to provide measurement access to delay characteristics of multiple high-speed NoC links in a 65 nm MPSoC. Therefore, a low frequency asynchronous sampling clock with relaxed jitter requirements can be used which simplifies integration and scalability.