Cluster Based Networks-on-Chip: An Efficient and Fault-Tolerant Architecture using Network Interface Assisted Routing

Cluster Based Networks-on-Chip: An Efficient and Fault-Tolerant Architecture using Network Interface Assisted Routing

Khalid Latif, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen
DOI: 10.4018/jaras.2013070102
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Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, the authors present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5×6 crossbar is used for the proposed architecture which requires one more 5×1 multiplexer without increasing the critical path delay of the router as compared to the 5×5 crossbar. The proposed router has been simulated for uniform, transpose and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.
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1. Introduction

Networks-on-Chip (NoC) has been proposed for System-on-Chip (SoC) based applications to achieve the better performance with lower power consumption as compared with typical on-chip bus architectures (Jantsch &Tenhunen, 2003).A typical NoC based system consists of processing elements (PE), network interfaces (NI), routers and channels. The router further contains switch, buffers and routing logic as shown in Figure 1. All links in NoC can be simultaneously used for data transmission, which provides a high level of parallelism. It is an attractive solution to replace the conventional communication architectures such as shared buses or point-to-point dedicated links by NoC.

Figure 1.

Conventional virtual channel NoC router architecture


Buffers consume the largest fraction of dynamic and leakage power of the NoC node (router + link; Banerjee, Vellanki, & Chatha, 2004). Storing a packet in buffer consumes far more power as compared to its transmission (Ye, Benini, & De Micheli, 2002). Thus, increasing the utilization of buffers and reduction in their number and size with efficient autonomic control reduces the area and power consumption. Wormhole flow control (William J. Dally, 2004) has been proposed to reduce the buffer requirements and enhance the system throughput. However, one packet may occupy several intermediate switches at the same time. This introduces the problem of deadlocks and live locks (Luca Benini, 2006). To avoid this problem the use of virtual channel is introduced. Virtual channel flow control exploits an array of buffers at each input port. By allocating different packets to each of these buffers, flits from multiple packets maybe sent in an interleaved manner over a single physical channel. This improves the throughput and reduces the average packet latency by allowing blocked packets to be bypassed.

A well designed network exploits available resources to improve performance with incurring minimum overhead (Balfour & Dally, 2006). Buffer utilization can be enhanced by sharing them with the other ports, when they are free. Router architecture with full sharing of buffers can deliver high throughput but at the expense of area and power consumption. On the other hand, architectures which does not share buffers consume less power but they provide lower throughput because the free buffers cannot be utilized by neighboring overloaded input channels. Hence, it is important to devise technique that enables judicious tradeoff between performance, power and area.

With the trend of technology and supply voltage scaling and increasing interconnect density; devices are exposed to a large number of noise sources such as capacitive and inductive crosstalk, power supply noise, leakage noise, thermal noise, process variations, charge sharing, and soft errors. Due to this, reliability of the manufactured devices is becoming endangered (Pasricha & Dutt, 2008; Lehtonen, 2009). There are a number of fault tolerant solutions available to deal with reliability at different abstraction levels for example routing algorithms (Lotfi-Kamran, Rahmani, Daneshtalab, AfzaliKusha, & Navabi, 2010; Z. Zhang, Greiner, & Taktak, 2008), architectures (Neishaburi & Zilic, 2009; Yaghini, Eghbal, Pedram,&Zarandi, 2010) and error control coding schemes (Frantz, Kastensmidt, Carro, & Cota, 2006; Shen, Huang, & Hsiung, 2010). Some of the fault tolerant NoC architectures proposed by researchers use intelligent routing algorithms (Fick et al., 2009; Dumitras & Marculescu, 2003). The key problem with this approach is that the fault-free resources which are interconnected with the faulty resource cannot be used. This inturn leads to a reduction in system performance. For instance, if there is a link failure in a VC based NoC, the VC buffers connected to the failed link cannot be used. Similarly, in case of router failure, PE connected to it cannot be used. To reduce the effect of fault on the system performance, such unused resources should be utilized by the system. A well designed network exploits all available resources to sustain performance (Balfour & Dally, 2006).

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