CompactRIO Based Real Time Implementation of AES Algorithm for Embedded Applications

CompactRIO Based Real Time Implementation of AES Algorithm for Embedded Applications

El Adib Samir (Remote Sensing & Geographic Information System Unit (RS&GIS), University of Abdelmalek Essaadi, National School for Applied Sciences of Tetuan, Tetuan, Morocco) and Raissouni Naoufal (Remote Sensing & Geographic Information System Unit (RS&GIS), University of Abdelmalek Essaadi, National School for Applied Sciences of Tetuan, Tetuan, Morocco)
DOI: 10.4018/IJERTCS.2019040102

Abstract

For real-time embedded applications, several factors (time, cost, power) that are moving security considerations from a function-centric perspective into a system architecture (hardware/software) design issue. The National Institute of Standards and Technology (NIST) adopts Advanced Encryption Standard (AES) as the most widely used encryption algorithm in many security applications. The AES algorithm specifies 10, 12 and 14 rounds offering different levels of security. Although the number of rounds determines the strength of security, the power consumption issue has risen recently, especially in real-time embedded systems. In this article, the authors present real time implementation of the AES encryption on the compactRIO platform for a different number of AES rounds. The target hardware is NI cRIO-9022 embedded real-time controller from National Instruments (NI). The real time encryption processing has been verified successfully. The power consumption and encryption time experimental results are presented graphically for 10, 12 and 14 rounds of processing.
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The AES algorithm is flexible in supporting any combination of data and key size of 128, 192, and 256 bits. Many researchers used different approaches have been used for the implementation on the basis of different technical acceptations which may be like AES strength execution, AES for efficiency or effectiveness execution, AES by hardware and software implementation and all that. Since then, many hardware implementations have been proposed in literature (Sklavos & Koufopavlou, 2002; Mangard et al., 2003; Hodjat & Verbauwhede, 2006; Mourad et al., 2007; Mozaffari-Kermani & Reyhani-Masoleh, 2012; Wang & Ha, 2013; Neelima & Brindha, 2018, Jayakumar, 2018). Some of them use Field Programmable Gate Arrays (FPGA) and others use Application‐Specific Integrated Circuits (ASIC). The first significant step in compacting the AES implementation was made when V. Rijmen proposed an AES hardware implementation based on composite fields (Jarvinen et al., 2003). A similar solution was proposed by J. Wolkerstorfer (2003). Rijmen’s idea has already been implemented in FPGA (2002), and in ASICs (Mayer et al., 2002; Wolkerstorfer et al., 2002; Rijmen, n.d.). Unfortunately, most of those implementations are too costly for practical embedded applications.

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