Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture

Introduction

Evolvable hardware (EHW) denotes the combination of evolutionary algorithms with reconfigurable hardware technology to construct self-adaptive and self-optimizing hardware systems (Higuchi et al., 1993; de Garis, 1993). EHW’s principle is the continuous optimization of its function to be able to react instantly to upcoming events. Several applications of EHW have been proposed, of which some have been very successful. Examples include data compression for printers (Tanaka et al., 1998), analog filters (Koza et al., 2004), evolved image filters (Sekanina, 2004), evolved shapes for space antennas (Lohn et al., 2004), and high performance reconfigurable caches (Kaufmann et al., 2009).

EHW-type adaptable systems improve their behavior in response to system internal and external stimuli, offering an alternative to classically engineered adaptable systems. While the adaptation to environmental changes represents the main research line within the EHW community, the ability to balance resources dynamically between multiple concurrent applications is still a rather unexplored topic. One the one hand, an EHW module might run as one out of several applications sharing a system's restricted reconfigurable resources. Depending on the current requirements, the system might decide to switch between multiple applications or run them concurrently, albeit with reduced logic footprints and reduced performance. We are interested in scalable EHW modules and architectures that can cope with such changing resource profiles. On the other hand, the ability to deal with fluctuating resources can be used to support the optimization process, for example by assigning more resources when the speed of adaptation is crucial.

In this work we study the capability of evolvable hardware to adapt to intentional run-time fluctuations in the available resources, i.e., chip area. To demonstrate our approach, we leverage the Functional Unit Row (FUR) architecture, a scalable and run-time reconfigurable classifier architecture introduced by Glette et al. (Glette et al., 2007a). We apply the FUR classifier on two medical benchmarks, the Pima and Thyroid data sets from the UCI Machine Learning Repository. While these benchmarks do not benefit from fast processing times, resource-efficient implementations and run-time adaptation of evolvable hardware, we consider them as model applications because they demonstrate nicely FUR's properties as fast recovery time, the ability to reach high accuracy rates using compact configurations and stable accuracy behavior under a wide range of parameters. We first investigate FUR's general performance for these benchmarks before examining classification behavior during architectural reconfigurations. To minimize the impact of architecture scaling, we introduce two reconfiguration techniques. The reconfiguration techniques gather statistical data during training phases and use it to select the basic pattern matching elements to duplicate or remove when changing the architecture size.

The paper is structured as follows: the next section presents the FUR architecture for classification tasks, its reconfigurable variant and the applied evolutionary optimization method. Benchmarks together with an overfitting analysis as well as the experiments with the reconfigurable FUR architecture are shown in the following section. The last section concludes the paper and gives an outlook on future work.

The Functional Unit Row Architecture

The Functional Unit Row architecture for classification tasks was first presented by Glette et al. (Glette et al., 2007a). It is an architecture tailored to online evolution combined with fast reconfiguration. To facilitate online evolution, the classifier architecture is implemented as a circuit whose behavior and connections can be controlled through configuration registers, similar to the approach of Sekanina (Sekanina et al., 2000). By writing the genome bitstream produced by a genetic algorithm (GA) to these registers, one obtains the phenotype circuit which can then be evaluated. In (Torresen et al., 2008), it was shown that the partial reconfiguration capabilities of FPGAs can be used to change the architecture’s footprint. The amenability of FUR to partial reconfiguration is an important precondition for our work. In the following, we present the organization of the FUR architecture, the principle of the reconfigurable FUR architecture, and the applied evolutionary technique. For details about the implementation of FUR we refer to (Glette et al., 2007a; Glette et al., 2007b).