Cooperative Encoding Strategy for Gate Array Placement

Cooperative Encoding Strategy for Gate Array Placement

Hong-Bo Wang (Sch. of Comp. and Commu. Engineering, University of Science and Technology, Beijing, China), Qing-Dong Su (Sch. of Comp. and Commu. Engineering, University of Science and Technology, Beijing, China) and Ruolei Zeng (Department of Computer Science, University of Wisconsin-Madison, Madison, USA)
DOI: 10.4018/IJSSCI.2018100103

Abstract

In recent years, the quadratic force-directed placement is becoming popular due to its stable quality at low power. The force-directed placement composes of two operations, namely, orientating and modulating. The two actions are going on until the overlap degree can meet a predetermined target. Different methods have a great influence on their quality of a layout. A novel encoding strategy of two-dimensional chromosome based on immune cooperative optimization is suggested. The main works first focus on a multi-point crossover strategy, and its Poisson distribution makes use of a Euclidean distance density between the concentration of antibody suppression and the translation variation of optimal gene pairs in two-dimension. Then, a flexible region division is proposed for dealing with the layout problem of gate array. The related experiment indicates the constructed encoding strategy for gate array placement is effective and efficient.
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Problem Descriptions

The core of IC gate array layout problem focuses on the optimal combination of gate array units, which means to place n units according to some patterns of gate array in order to meet different constraints of integrated demand (Tim, 2011; Stephen, 1992).

Some Definitions

The information determined in the stage of circuit design before gate array layout includes the following: (1) The unit number of gate array n, the height of each gate array unit hi and the width of each gate array unit; (2) Coordinates of gate array unit I/O pins; (3) A set of gate array line network L. Coordinates of each I/O pins where every line network linked to. (4) The height H and width W of gate array layout zone. Number of lines r which layout zone been divided into and the height of each line hr().

Each gate array line network Li can be linked to two or more gate array units Ai or pins Pi, a gate array unit Ai or pin Pi belongs to multiple gate array line networks.

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