Design of an Intelligent Data Cache with Replacement Policy

Design of an Intelligent Data Cache with Replacement Policy

B. Shameedha Begum (National Institute of Technology Tiruchirappalli, Tiruchirappalli, India) and N. Ramasubramanian (National Institute of Technology Tiruchirappalli, Tiruchirappalli, India)
DOI: 10.4018/IJERTCS.2019040106

Abstract

Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.
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2. Overview Of Existing Systems

Embedded Systems, it is the craft of picking and planning the correct combination of equipment and programming parts to attain outline objectives like speed and efficiency. The embedded systems which have hard real-time constraints are used for focused categories of applications. Performance of processor and cache are of immense importance to meet those time constraints. Also, cache contributes to performance optimization of embedded processors. Hence there is a need to optimize cache performance.

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