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In general, a digital signal processing system requires Digital-to-Analog Converter (DAC) at the end because human beings understand the processed output in analog form only in Figure 1. The desired characteristics of DAC are low power dissipation, high accuracy, good reliability, linearity, and so on. DAC is also required in the design of a high-resolution two-stage analog to digital converter (ADC) (Banoth, et al., 2021).
Different architectures of DAC include current steering, charge scaling, voltage scaling, and binary-weighted steering. Binary weighted steering architecture has been found most cost-effective and best suited for high-speed applications (Yu-Lan et al., 2020).In this type of DAC, to create the reference current, the DAC employs a weighted current, DAC employs a weighted current source generated by current mirrors, and MOS transistor switches adjust the current. The input bits control the switches, as indicated in “Figure 2.” (Piyush Mathurkar, et al., 2015). Every weighted current source is weighted by 20, 21, 22, 23, 2N where N represents the number of bits.
The demonstration needed of the DACs in these frameworks will be influenced by the abilities and demands of various parts of the framework. A DAC generates a quantized (discrete advance) simple result due to a paired digital input code. TTL, ECL, CMOS, or LVDS can be utilized as digital inputs, and the basic result can be either a voltage or a current. A reference value is split into twice and straight segments to get the result. The digital input controls switches that link a variety of components to determine the outcome. For N bits, there are feasible codes. The analog output of the DAC is the discrete fraction represented via way of means of the ratio of discrete enter code divided via way of means of 2 instances of the analog reference value.Standard signs are time-sensitive signs with a limitless goal and hypothetically limitless information transmission. The DAC's outcome, then again, is a sign comprised of discrete properties (quantization) estimated across standard yet appreciative periods (sampling). To put it another way, the DAC yield attempts to manage an essential sign that has a confined point and information move limit. Quantization and testing drive the key, though surprising, requirements of DAC execution. Quantization, which causes quantization error or commotion in the result, characterizes the converter's biggest one-of-a-kind extension. As indicated by the Nyquist model, assessing describes the DAC yield's quickest move speed.
To prevent test images from happening in the DAC yield's repeat space, the Nyquist standard expresses that the sign repeat will not be unequivocally or similar to one-a significant part of the testing repeat. The basic yields of an ideal DAC are confined by precisely one least huge piece (LSB), where one LSB approaches the full-scale straightforward yield adequacy isolated by 2, and N is the DAC objective communicated in bits. Nonideal components have an impact on the value of DACs, with little regard paid to the impacts coordinated by quantization and testing. An assortment of elements impacts the execution of static or DC code. The distinction between the incline of the converter's trade work and the ideal trade work is characterized as a acquire error. When the increment error is zero, the offset error is the difference between the DAC output and the ideal response work. Differential nonlinearity (DNL) is the departure of the true development size from the optimal 1-LSB (least significant bit) venture at each data code. DNL errors may cause further material disruption and spikes as a result of prior quantization impacts.