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TopAnagnostopoulos et al. (Anagnostopoulos et al., 2011) perform microcode optimizations for the DMM of an MPSoC through a hardware-based dual-microcoded controller. A dynamic multithreaded application is statically analyzed to obtain DMM decision trees, where exploration is performed based on a constraint-orthogonal partition methodology, similar to (Atienza, Mendias, Mamagkakis, Soudris, & Catthoor, 2006; Xydis, Bartzas, Anagnostopoulos, Soudris, & Pekmestzi, 2010). Variable sized and types of heaps, with local or global visibility (w.r.t other cores), can be refined for different MPSoC topologies. However, allocations made to local or global heaps are at most 1500 bytes in size and are stored in SDRAM. Therefore, in order for an application to manage larger dynamic allocations, a large amount of SDRAMs would be consumed.
Atienza et al. (Atienza et al., 2006) present a methodology for the management of memory and the reduction of the footprint of dynamic memory allocations for embedded multimedia and wireless applications. Fragmentation was found to impact the memory footprint of systems and was reduced by applying their memory management methodology, albeit with an increase in execution time.
Koutras, Bartzas, and Soudris (Koutras, Bartzas, & Soudris, 2012) investigate the use of adaptive dynamic memory allocators to predict the amount of memory an application might want. Runtime information is used to ascertain the current memory requirements of the application and the current state of memory space. A goodness factor is used to predict future memory accesses and how blocks are allocated.
Xydis et al. (Xydis et al., 2010) define a design space for multithreaded DMM for MPSoCs and explore it to find the optimal solution. They extend a previous single-threaded DMM design space model (Atienza et al., 2006) and capture multiprocessor and multithreaded decisions. However, the work assumes the presence of an OS to manage heaps for threads and the MPSoC which is quoted as being an Intel Quad Core MPSoC operating at 2.66 GHz, making it uncertain of the applicability to embedded systems.