Efficient Low-Power Compact Hardware Units for Real-Time Image Processing

Efficient Low-Power Compact Hardware Units for Real-Time Image Processing

Khaldoon M. Mhaidat (Computer Engineering Department, Jordan University of Science and Technology, Irbid, Jordan), Mohammad I. Alali (Computer Engineering Department, Jordan University of Science and Technology, Irbid, Jordan) and Inad A. Aljarrah (Computer Engineering Department, Jordan University of Science and Technology, Irbid, Jordan)
DOI: 10.4018/ijitwe.2014100103
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Abstract

This paper presents efficient low-power compact hardware designs for common image processing functions including the median filter, smoothing filter, motion blurring, emboss filter, sharpening, Sobel, Roberts, and Canny edge detection. The designs were described in Verilog HDL. Xilinx ISE design suite was used for code simulation, synthesis, implementation, and chip programming. The designs were all evaluated in terms of speed, area (number of LUTs and registers), and power consumption. Post placement and routing (Post-PAR) results show that they need very small area and consume very little power while achieving good frame per second rate even for HDTV high resolution frames. This makes them suitable for real-time applications with stringent area and power budgets.
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Introduction

Real-time image and video processing will always be essential in many applications (Chillet & Hübner, 2014; Sahlbach, Thiele, & Ernst, 2014; Baxes, 1994; Gonzalez & Woods, 2007; Nixon & Aguado, 2012). Examples include real-time medical imaging (Birk, Zapf, Balzer, Ruiter, & Becker, 2014), multimedia wireless sensor networks (Taysi, Yavuz, Guvensan, & Karsligil, 2014), automated surveillance (Ratnayake & Amer, 2014), pattern recognition (Brost, Yang, & Meunier, 2014), automated industrial visual inspection (Vega-Rodríguez, Sánchez-Pérez, & Gómez-Pulido, 2002), and high-definition video streaming (Hoffmann, Itagaki, Wood, & Bock, 2006; Elhamzi, Dubois, Miteran, & Atri, 2014). Therefore, there will always be a great need for efficient ways to perform image and video processing at real-time speed while satisfying sometimes stringent quality, area, and power requirements as in the case of embedded systems (Chillet & Hübner, 2014). For example, H.264 is one of the most popular video compression formats and requires a large amount of computations. Therefore, different architectures and techniques can be explored to come up with efficient implementations as in the H.264-compatible motion estimation accelerator presented in (Elhamzi, Dubois, Miteran, & Atri, 2014).

In general, there are four ways to implement image and video processing algorithms: Software running on general-purpose microprocessors/CPUs or microcontrollers, software running on specialized graphics processing units (GPUs) or digital signal processors (DSPs), hardware implemented in field-programmable gate arrays (FPGAs), or hardware implemented in application-specific integrated circuits (ASICs; Nelson, 2000; Johnston, Gribbon, & Bailey, 2004; da Silva, et al., 2013; Ratnayake & Amer, 2014; Sahlbach, Thiele, & Ernst, 2014).

Image and video processing software will be slow when run on general-purpose processors and controllers because these devices are designed to handle many other functions or tasks and not designed specifically or solely for image and video processing. Moreover, they are generally serial (or sequential) in the way they run the code. Even a multi-core multi-threaded processor will not fully utilize or exploit all the parallelism inherent in image and video processing algorithms due to various reasons including memory and I/O sharing and threads communication overhead not to forget the serial nature of a the individual threads. GPUs will be faster than CPUs because they have been designed mainly for graphics processing but they will still be slower than a dedicated image and video processing hardware since they need to support a large set of general graphics processing functions.

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