Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems

Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems

Kameswar Rao Vaddina (Turku Center for Computer Science (TUCS), Turku, Finland & Department of Information Technology, University of Turku, Turku, Finland), Pasi Liljeberg (Department of Information Technology, University of Turku, Turku, Finland) and Juha Plosila (Department of Information Technology, University of Turku, Turku, Finland)
DOI: 10.4018/jaras.2013070104
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Abstract

Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping.
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Introduction

As the technology scales down, the ability to manufacture and operate billions of transistors and run them at high operating frequencies has become easier. But, an important reliability concern has been emerging lately from the combination of increased device power density and ambient environmental conditions thereby leading to high operating temperatures of the system. The increase in power density also leads to an increase in a lot of parameters like power dissipation, leakage, data activity and electro-migration contributing to higher temperatures, larger temperature cycles and increased thermal gradients all of which impact multiple failure mechanisms (“The International Technology Roadmap for Semiconductors (ITRS)”, 2007). This increase in temperature, increases interconnect delay due to the linear increase in electrical resistivity. These delay variations pose significant reliability problems with already dense interconnect structures. Also, instantaneous high temperature rises in the devices can possibly cause catastrophic failure, as well as long-term degradation in the chip and package materials, both of which may eventually lead to system failure (“Flip Chip Ball Grid Array Package Reference Guide”, 2005).

Thermal problems are exacerbated with the transition from 2D chip systems to 3D stacked system. Recently, three-dimensional (3D) integrated circuits have been proposed which would overcome the problems associated with the interconnects and the limits being posed by the traditional CMOS scaling. 3D integrated circuits take advantage of dimensional scaling approach and are seen as a natural progression towards future large and complex systems. They increase device density, bandwidth and speed. But on the other hand, due to increased integration, the amount of heat per unit footprint increases, resulting in higher on-chip temperatures and thereby degrading the performance and reliability of the system. In this case, heat sinks need to be very efficient in transferring the internally generated heat to the ambient. Most modern flip-chip devices are designed to operate reliably with a junction temperature falling under a certain range. To ensure that the package can perform well thermally under this range a thermal model is simulated and tested. This thermal model can then be used to gauge the reliability of the package. This shortens the package development time and also provides an important analytical tool to evaluate its performance under different operating conditions.

The ITRS report projects that the power density for 14nm technology node will be greater than 100W/cm2 and the junction-to-ambient thermal resistance will be less than 0.2°C. It is very important to keep the thermal resistance at bay as this may increase the package cost and the overall cost of the product. Observation of the thermal contours of certain industrial chip shows that the temperature at the hotspots can exceed 100°C (Tsai et al., 2006).

One way to address the high and uneven distribution of temperatures on the chip is to make sure that the circuit blocks are placed in such a way that they even out the temperature profile of the system by using thermal-aware placement techniques. Simplistically, if we distribute high power blocks evenly across the chip the temperature profile will be uniform and hotspot related thermal issues can be mitigated (Tsai et al, 2006). But, in practice, the thermal placement is a more complex problems and uniform distribution of power does not lead to uniform temperature profile as can be seen in Section Thermal-aware placement approaches in 2D and 3D chip systems. This work forms the basis of such an algorithmic technique by arriving at metrics which can be used at design time to evenly distribute the high temperature blocks across the chip with very low overhead.

Guoping et al. (Xu, Guenin, & Vogel, 2004; Xu, 2006) have done thermal modeling of multicore systems and have investigated the effects of CPU power level, local hotspot power density, hotspot location and hotspot size on its thermal performance. But they stopped short of extending their work to 3D multicore systems. Ankur et al., (Jain, Jones, Chatterjee, & Pozder, 2010) have proposed an analytical and numerical modeling of the thermal performance of three-Dimensional Circuits. In this paper we present an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping.

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