High Throughput Realization of a New Systolic Array based FFT using CORDIC

High Throughput Realization of a New Systolic Array based FFT using CORDIC

Gourav Jain (Center for Development of Telematics, Bengaluru, India) and Shaik Rafi Ahamed (Department of E.E.E., Indian Institute of Technology, Guwahati, India)
DOI: 10.4018/ijmtie.2012040105
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In this paper, the authors propose a new systolic array for radix-2, N-point discrete Fourier Transform (DFT) computation based on CORDIC (CO-ordinate Rotation Digital Computer). Complex multiplication can be done by this in a rather simple and elegant way. A CORDIC based multiplier less DFT architecture is designed in order to improve the performance of the system. It is able to provide two transforms per each clock cycle. The proposed design is well suited for high speed DSP-applications.
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2. The Algorithm For Fft-Computation

Firstly we take review of the FFT-algorithm presented in (Choi & Boriakoff, 1992). Now N-point DFT is defined by:

(1) where N is a power of two and twiddle factor ijmtie.2012040105.m02

We can also rewrite above equation as followsY =W(N)X(2) whereInput vector X = [x0,x1,x2, …… xN-1]TOutput vector Y = [y0,y1,y2, …… yN-1]Tand transformation matrix


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