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In the sixties', the great advances in the semi-conductor technology allowed the integration of millions of transistors on a small chip of silicon enabling the emergence of what it is called System on Chip or SoC. The latter replaced traditional well-known Systems on Board (SoB), offering a more practical and cost-effective solution for embedded systems implementation.
According to Moores' Law, the number of the integrated transistors is doubling each 18 months thus SoC design and verification are becoming more complex and errors-prone. Moreover, the complexity of such systems is growing year by year while the productivity of hardware and software developers is not growing at a comparable pace as shown in Figure 1. To reduce this productivity gap and to meet time to market requirements, an efficient and inevitable solution was adopted; it is the reuse of a preexisting (designed in earlier projects or supplied by external vendors) and verified elements (intellectual property).
Figure 1.
Productivity gap (Menhorn and Slomka, 2013)
An intellectual property (IP) is a hardware or a software electronic component, it could be hard (couldn't be modified), firm (with a restricted possibilities of modification) or soft (with a large possibilities of modification). The IP may be provided by a third party who creates and qualifies it to be used by another person or team of work. The IP should be also classified in catalogs on the web. The IP integrator, called also SoC architect or simply the SoC designer, chooses the suitable IP for his SoC and integrates it with the other components (IPs) in his design. The process of IP reuse with more details is shown in Figure 2.
Figure 2.
IP reuse process (Wagner, 2004)
After their creation, qualification using some attributes and classification it in a web catalog, the system on chip architect (the integrator) could search IPs, validate them then integrate them in his SoC design. Since IPs are delivered by different providers, it is highly possible that they are either written in different languages (e.g. VHDL, Verilog, SystemC, etc.) or in merely one standard language but at different levels of abstraction (e.g. SystemC Transactional level, RTL, logic, etc.). Besides, they may use different interfaces and protocols, and so a great effort is needed to integrate them in one SoC meeting the functional and the QoS requirements.
The integrator needs to know sufficient information about the IPs he intends to integrate in his SoC. However, before 2009, IPs providers give information about their IP in different way, there are no rules or norms which define which information should be provided for an efficient integration process. From here comes the need to unify the amount of information provided about the IP and the format in which the information is provided. This information is called metadata and it was seen as the key of any attempt to enhance IP integration process. Thus, the standard IPXACT emerges in 2009 to unify the amount and the format of the IP machine readable metadata and so enables an easier, faster and less prone errors integration of IPs. The standard describes, in XML format, IPs interfaces and so defines many integration possibilities with other information about quality test benches as well as other useful information about the IP packaging files which will facilitate the IP configuration and instantiation.
Over the years, many solutions and practices have been adopted to facilitate the tasks of the integrator hence challenges changes from time to another accordingly. This paper tries to reveal the major challenges faced by the integrator as well as the solutions proposed by both academia and industry. The paper is organized as follows: preceded with a definition of IP integration problematic, the paper presents the related works divided into two categories those before the emergence of the standard IP-XACT and the others after IP-XACT emergence. The paper concludes by a proposition of model driven engineering as a promising solution to IP integration problematic.