Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

Sanna Määttä (Tampere University of Technology, Finland), Leandro Möller (Technische Universität Darmstadt, Germany), Leandro Soares Indrusiak (University of York, UK), Luciano Ost (Catholic University of Rio Grande do Sul, Brazil), Manfred Glesner (Technische Universität Darmstadt, Germany), Jari Nurmi (Tampere University of Technology, Finland) and Fernando Moraes (Catholic University of Rio Grande do Sul, Brazil)
DOI: 10.4018/jertcs.2010103005
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Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.
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This article is based on the premise that it is necessary to consider the impact of the application on its underlying platform early at the design process in order to meet all performance, area, power consumption, and time-to-market constraints. Many research initiatives are also built on that premise, especially in multiprocessor System-on-Chip (MPSoC) design. Some of them are detailed below.

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