Lightweight VLSI Architectures for Image Encryption Applications

Introduction

Data encryption through cryptographic algorithms has been the widely adopted mechanism to offer data confidentiality. Majority of security techniques ranging from high end to low end applications choose Advanced Encryption Standard (AES) algorithm to offer privacy. Mathematical complexity of AES may not be a suitable choice to the ubiquitous, smart and compact systems. National Institute of Standards and Technology (NIST) recommends the creation of portfolio of recently announced lightweight cipher suites which are mathematically less complex (McKay, et. al., 2017). Several federal security agencies also aim towards exploration of both software and hardware implementation aspects of lightweight cipher definitions to promote their real time applications. Lack of significant amount of the variety of hardware implementation of the lightweight algorithms hinders its usage in edge applications.

S-box is the only non-linear component in the block cipher algorithms and its efficient design paves way to major architectural variations, which leads to performance efficiency and less area overhead. Literature highlights that the finite field, combinational, S-box structure design approach of AES block cipher implementation has been the primary reason behind the better performance and less resource occupation and it has also been exhaustively analyzed. Popular AES S-box design approaches based on finite fields have been highlighted below.

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  A low-power S-Box circuit with a multi-stage PPRM architecture over composite fields has been proposed in (Morioka et. al., 2002)

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  Choice of combinational logic only mechanism for hardware implementation of Advanced Encryption Standard (AES) algorithm with SubBytes and InvSubBytes transformations led to several advantages, namely, the elimination of unbreakable delay incurred by look-up tables in the conventional approaches, the advantage of sub-pipelining, the design with composite field arithmetic to reduce the area requirements, and possibility of different implementations for the inversion in subfield GF(2⁴) (Zhang X, et. al., 2004)

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  S-box implementations results shown by (Tillich et. al., 2008) show the dedicated low-power implementations with good timing properties and offer the best power-delay and power-area product

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  All feasible constructions for the composite Galois field GF(((2²)²)²) Advanced Encryption Standard (AES) S-box into four main architectures by their field representations and their algebraic properties and a common sub-expression elimination effectively reduces the total area gate count as well as the critical path gate count in composite field AES S-boxes. The resulting architecture achieves maximum reduction in both total area coverage and critical path gate count (Wong et. al., 2011)

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  (Raghuram et. al., 2016) presented the implementation of Rijndael S-Box using combinational logic for the SubByte transformation in the Advanced Encryption Standard algorithm in semi-custom ASIC technology

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  Composite field arithmetic (CFA)-based S-box, with common sub-expression elimination (CSE)–shortest critical path constructing (SCPC) algorithm has minimal area cost and also the shorter critical path in both theoretical computing evaluation and experimental evaluation (Zhang et. al., 2016)