Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm

Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm

Hoang Trang (University of Technology, Vietnam National University Ho Chi Minh City, Ho Chi Minh City, Vietnam) and Nguyen Van Loi (IC Design Research & Education Center, Vietnam National University Ho Chi Minh City, Ho Chi Minh City, Vietnam)
Copyright: © 2013 |Pages: 22
DOI: 10.4018/jdst.2013010105
OnDemand PDF Download:
$30.00
List Price: $37.50

Abstract

This paper presents a Field-Programmable Gate Array (FPGA) implementation of an Advanced Encryption Standard (AES) algorithm using approach of combination iterative looping and Look-Up Table (LUT)-based S-box with block and key size of 128 bits. Modifications in the way of loading data out in AES encryption/decryption, loading key_expansion in Key_Expansion blocks are also proposed. The design is tested with the sample vectors provided by Federal Information Processing Standard (FIPS) 197. The design is implemented on APEX20KC Altera’s FPGA and on Virtex XCV600 Xilinx’s FPGA. For all the authors’ proposals, they are found to be very simple in FPGA-based architecture implementation, better in low latency, and small area, but large in memory, moderate throughput.
Article Preview

Introduction

For a long time, the Data Encryption Standard (DES) with a key length of 56 bits was considered as a standard for the symmetric key encryption. However, this key length was considered small and could easily be broken. For this reason, the National Institute of Standards and Technology (NIST) opened a formal call for algorithms in September 1997. After careful selection and evaluation processes, on October 2, 2000, NIST announced that the Rijndael algorithm of two inventors Joan Daemen and Vicent Rijmen was the winner. Rijndael algorithm can be specified with key and block sizes in any multiple of 32 bits, with a minimum of 128 bits and a maximum of 256 bits. Therefore, the problem of breaking the key becomes more difficult (Daemen & Rijmen, 2002; Tessier & Burleson, 2001; Bertoni, Guajardo & Paar, 2004; Boklan, 2009; Al-Hamdani, 2009). In cryptography, the Advanced Encryption Standard (AES) is the name of the standard, but in practice, Rijndael algorithm is also referred to as AES (FIPS PUB 197, 2001). AES has a fixed block size of 128 bits and a key size of 128, 192 or 256 bits.

The AES algorithm can be efficiently implemented by hardware and software. Software implementations cost the smallest resources, but they offer a limited physical security and the slowest process. Besides, growing requirements for high speed, high volume secure communications combined with physical security, hardware implementation of cryptography takes place. In contrast to software implementation, the pure hardware implementation could provide higher security and the higher data rate (Gbits/second) by pipelining and parallelization (Verbauwhede, Schaumont & Kuo, 2003), and also provides a cost-effective solution for many application specific systems.

An FPGA implementation is chosen in this study since it is an intermediate solution between general purpose processors (GPPs) and application specific integrated circuits (ASICs). It has advantages over both GPPs and ASICs in which FPGA provides a faster hardware solution than a GPP; wider applicability than ASICs since FPGA is more flexible, and small development cost (Liu, Lu, Kuehn & Jantsch, 2012; Shih & Hsiung, 2009; Imran et al., 2012).

This paper deals with an FPGA implementation of an AES encryptor/decryptor using an iterative looping approach with block and key size of 128 bits. Besides, our design uses the lookup- table (LUT) implementation of S-box in AES algorithm. The proposed approach of combination iterative looping and LUT-based S-box is chosen since it gives very low complexity architecture and is easily operated to achieve low latency as well as moderate throughput (Hoang & Nguyen, 2012). In the our previous work (Hoang & Nguyen, 2012), it is shown that the combination of iterative looping and LUT-based approach provides low latency of 13 clock cycles in encryption, 23 clock cycles in decryption which is lower than other works (Panato, Barcelos & Reis, 2002; Atul, Borkar, Kshirsagar & Vyawahare, 2011; Elbirt, Yip, Chetwynd & Paar, 2000; McLoone & McCanny, 2001; Standaert, Rouvroy, Quisquater & Legat, 2003; Saggese, Mazzeo, Mazocca & Strollo, 2003). The iterative looping and LUT-based S-box approach also gives smaller area, moderate throughput but large in memory (Hoang & Nguyen, 2012). This paper is an extended version of our previous work (Hoang & Nguyen, 2012), but in this study, we are aiming to improve the latency in our AES design on FPGA since speed is an important issue beside of security mean while these two issues play in the favour of the hardware implementation of encryption/decryption applications.

Complete Article List

Search this Journal:
Reset
Open Access Articles
Volume 10: 4 Issues (2019): Forthcoming, Available for Pre-Order
Volume 9: 4 Issues (2018): 1 Released, 3 Forthcoming
Volume 8: 4 Issues (2017)
Volume 7: 4 Issues (2016)
Volume 6: 4 Issues (2015)
Volume 5: 4 Issues (2014)
Volume 4: 4 Issues (2013)
Volume 3: 4 Issues (2012)
Volume 2: 4 Issues (2011)
Volume 1: 4 Issues (2010)
View Complete Journal Contents Listing