Low Power Restoration Circuits Reduce Swing Voltages of SRAM Cell With Improved Read and Write Margins

1. Introduction

Low power Static Random Access Memories have become a critical component of many VLSI chips. This is especial consideration for microprocessors where the on chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processors and the main memory (P. Barnes 2010, S. Hesley, et.al, 2009). one of the major issues in the design of an SRAM cell in stability. The cell stability determines the sensitivity of the memory to process tolerances and operating conditions.

The stability of Static Random access memory cell in the presence of DC noise is measured by the static noise margin (SNM). Static Noise Margin is the amount of voltage noise required at the output nodes to flip the state of the cell. This can be obtained using using the voltage transfer characteristic (VTC) of the two cross coupled inverters of the SRAM cell (Seevinck et al., 1987).

Figure 1 illustrates the schematic of a 6 transistor SRAM cell for simulating the static noise margin. The sources Vn are the noise sources at the state nodes of the cell (Pavlov & Sachdev, 2008).

Figure 1.

Schematic of a 6T SRAM bit cell with noise voltage sources for measuring SNM (Seevinck et al., 1987)

The cross-coupled inverters maintain a bi-stable state and their output nodes retain the data stored in the cell. However, as the noise Vn increases, the stability of the cell degrades because of the fluctuations at the node voltages. The Static Noise Margin quantifies the allowed levels of these noise voltages and thus the ability of these inverters to retain their state in the presence of noise.

The goal of this paper is to determine the effect of several circuit parameters on the SNM of the 6T SRAM cell designed in 180-nm CMOS process technology and compare it with the model derived in (Seevinck et al., 1987).

The SNM of the SRAM Cell When in standby or retain mode, read operation, and write operation. The SNM of the SRAM cell is obtained by plotting the VTCs of the Two cross-coupled inverters. The VTC of one of the inverters is flipped with respect to the line y = x in order to form a “butterfly curve”. The SNM is the side of the smaller square that can be fitted inside the “eye” of the graph as shown in Figure 1 (Seevinck et al., 1987).

Figure 2.

Schematic of a 6T SRAM bit cell and sample SNM-the side of the largest square fitted inside the graph (Calhoun & Chandrakasan, 2006)

This Paper is organized as follows: the characteristics of 6T SRAM cell are described are represented in section II. In section III, Proposed 8T SRAM cell is described. In section IV, Standard 8T SRAM cell is described. Section V includes the simulation results which give comparison of different parameters of 6T and 8T SRAM cells and section VI conclusion the work.

2. Six Transistor (6T) Sram Cell

In a conventional 6T SRAM cell, the data storage nodes are directly accessed through the bit-line access transistors during read operations, as shown in Figure 1. While reading, the storage node voltages are disturbed between cross-coupled inverter pair and bit lines. The BL and BLB are the bit lines and WL is the word line. The access transistors are controlled by WL (word line) to perform the operation of read and write operation. Bit lines act as input and output nodes. During a read operation, bit lines transfer the data from SRAM cells to a sense amplifier. Based on the technology the minimum length of the transistors is 180nm (Seevinck et al., 1987).

Figure 3.

6T SRAM Cell (Seevinck et al., 1987)