Method for Improving Data Security in Register Files Based on Multiple Pipeline Restart

Method for Improving Data Security in Register Files Based on Multiple Pipeline Restart

Qingyu Chen, Longsheng Wu, Li Li, Xuhan Ma, Xu An Wang
DOI: 10.4018/IJITWE.2015070102
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Data security in the register file significantly decreases as a result of technology scaling. Based on pipeline restart, the method of improving the data security and reliability in register files is presented in this paper. As the data and its replica simultaneously exist as a redundant copy of each other in half-custom register files, when an uncorrectable error is detected in the data during the access of the register file, its replica will be checked for subsequent processor operation by the restart of pipeline. In addition, the correctable error in data or its replica can also be scrubbed by rollback and restart of pipeline. Finally, the proposed method is evaluated and the results show that the hardware overhead increases by only 2%, whereas the reliability of data in register file increases by more than 2.5 times. This method can significantly improve the data security in the register file without distinct overhead increasing.
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1. Introduction

With the scaling of IC (integrated circuit) technology, the memory bit upset is more likely caused by high-energy particles from environment and packaging materials. Thus the data security and reliability in memory poses an increasing challenge in recent years (Hareland, 2001; Karnik, 2001; Mukherjee, 2004; Mavis, 2008).

The register file based on synchronous RAM (Random Access Memory) can be considered as the highest level storage in the memory hierarchy of a processor (Hamacher, 2012; Yuan, 2014). As the temporary data storage node between cache and processor, the register file often holds data for long periods of time and is read frequently (Memik, 2005; Montesinos, 2007), which not only increases the SEU (Single Event Upset) probability of data in register file but also contributes to spread a faulty datum to other parts of processor. For these reasons, transient errors occurring in a register file in most cases result in a failure of system program (Fazeli, 2008). Therefore, the register file is the most vulnerable to SEU effect in the processor from a reliability point of views (Abazari, 2012). To enhance the security and reliability of the data in register file, many studies have been conducted.

For the full-custom register file, the data reliability is significantly associated with the radiation-hardened design of the storage cell and peripheral circuit. The Dual Interlocked storage Cell (DICE) and modified DICE have been presented to mitigate the SEU in storage cells of SRAM (Static Random Access Memory)(Sun, 2012). The double module redundancy method and C-element structure based on time redundancy are also proposed to resolve the upset in the peripheral circuit (Sun, 2012; Song, 2012). The full-custom radiation-hardened register file can absolutely improve the anti-upset ability of storage cell. However, its development needs parameter extraction, model and optimization iteration, all which inevitably induce extra power consumption and access latency. Therefore, those unfavorable factors limit the application of full-custom radiation-hardened register file in the high performance and low power processor.

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