Performance Analysis of On-Chip Communication Structures under Device Variability

Introduction

As transistor gate lengths continue to shrink according to Moore’s law (Moore, 1965), designers are now able to incorporate complete systems with complex functionalities in a single System-on-Chip (SoC). As a result, Embedded System design is migrating from board level integration to on-chip level integration, where components are often-times developed by third parties and integrated by the system designer. The increase in complexity of these systems has introduced a number of challenging problems in the design, project management, simulation and verification of these devices. For instance, according to the ITRS (ITRS, 2003), as the technology scales, the devices are increasingly becoming faster relative to the interconnect. Therefore, modern SoC and Embedded designers are faced with the difficult task of orchestrating the computation of a large number of fast local third party hardware blocks, across the whole chip, by using (relatively) progressively slower interconnects. Consequently, on-chip communication is rendering major constraints to the performance of the system.

Network-on-Chip (NoC) has been proposed as a suitable design methodology (Benini & Micheli, 2002; Dally & Towles, 2001) for modern SoCs which offers an interconnect-centric system architecture to manage the problems of on-chip communication. It works as a small on-chip communication network consisting of typical communication layers such as physical, data link, network, transport and application, each one geared for particular functions. The design of the physical layer is of vital importance as it provides a physical communication media from router-to-router and from router-to-functional units (FUs) for the exchange of data between them. The global interconnect between the routers and semi-global interconnect between the routers and functional units put many challenges for designing them for high performance, especially in deep sub-micron region (Lee & Yoo, 2004). These communication links can either be (a) multi-bit parallel, (b) partially parallel where an n-bit packet or flit is divided in to a small number of m-bits or (c) source-synchronous serial (Kim & Sobelman, 2006).

The increase in clock speed and chip size means that synchronization can no longer be obtained by the use of a global clock, and that other models of synchronization (such as the use of multiple clock domains or by the Globally Asynchronous Locally Synchronous (GALS) approach) are required. Effectively the maximum synchronous area is determined by the clock skew. The individual synchronous blocks can communicate with each other synchronously, asynchronously or in a self timed manner. In this paper, we have chosen to focus on cross clock domain communication structures, since due to their high performance and low design effort, it is likely that they will be used in future designs, in which an overlap of different synchronous blocks on the chip communicate with each other synchronously. However, these structures are not completely immune to skew which can develop in the global clock and wide data communication links.