Performance Analysis of Temperature Management Approaches in Networks-on-Chip

Introduction

The emergence of nanotechnology is accompanied by cumulative power densities and switching activities per unit area. Therefore, increasingly complex and highly integrated systems like SoCs have to contend with well-known challenges. Amongst others, this concerns heat dissipation, leading to high circuit temperatures and possibly strongly unbalanced on-chip temperature distributions (see ∆T [°C] in Table 7 for examples regarding on-chip temperature variations). In the light of a growing number of transistors per chip, which are increasingly susceptible to environmental influences and deterioration, this issue is topical more than ever. As a consequence, thermal stress and physical effects exponentially depending on temperature (JEDEC, 2009) threaten the integrity of Integrated Circuits (ICs) and have major influence on operability, lifetime and performance. The relationship between temperature and deterioration is illustrated by the Arrhenius model (Srinivasan & Adve, 2003) describing the influence of temperature on the velocity of chemical reactions. This model originates from the Van’t Hoff rule also known as the reaction rate temperature rule (or RGT rule), saying that chemical reactions take place twice as fast when temperature is increased by 10 K. As a rule of thumb, this also can be interpreted as a bisection of lifetime of ICs with every 10 K temperature increase. For this reason, monitoring and control of on-chip temperature distribution are important tasks to secure system functionality and ensure high performance.