Qualitative Analysis of 3D Routing Algorithms in 3×3×3 Mesh NoC Topology Under Varying Load in Bio-SoC

Qualitative Analysis of 3D Routing Algorithms in 3×3×3 Mesh NoC Topology Under Varying Load in Bio-SoC

Nidhi Syal (Uttarakhand Technical University, Dehradun, India) and Vivek Kumar Sehgal (Jaypee University of Information Technology, India)
Copyright: © 2020 |Pages: 17
DOI: 10.4018/IJEHMC.2020070106


This article presents a qualitative analysis of a 3D routing algorithm in a 3×3×3 mesh NOC topology. The effect of load variation on throughput, total energy, and maximum delay for different types of routing is observed. The simulation was performed on an Access NOXIM network-on-chip simulator under random traffic conditions. The research involves quality parameters like total packets received, total received flits, global average delay (cycles), global average throughput (flits/cycle), throughput (flits/cycle/IP), max delay (cycles), total energy (J), average power (J/cycle), average power per router (J/cycle), and average waiting time in each buffer. In this article, it was observed after comparing all the routing techniques against the mention parameters the XYZ routing techniques was found perform better followed by West first, and North last, while poor performance was observed against odd-even, negative first, and fully adaptive.
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1. Introduction

A fast and smart biomedical DAS is composed of many integrated IPs and scaled interconnects. Many smart sensors are either integrated within the chip in the form of an IP block or connected through the smart interface. The logged data is communicated through internet enabled integrated IP. The multilayer 3D system on chip is the best on-chip clinic solution, Where the sensing row is for getting the data from various biomedical sensors, the middle row is to log the data and generate the actuating signals for remote surgery through robotic hands. The last layer of the architecture contains the set of IP cores of outer actuators interface through the internet, Bluetooth and wi-fi modules. The scaled SoC architecture for biomedical applications is very crucial for real time applications. So, the routing algorithms should route the packets with improved quality of services. Expansion of new ports in the router can vanquish issue of obliged data transfer capacity and scaling. 3D NoC, architecture created using various uniform silicon planes and each unique plane is a 2D mesh topology associated with vertical connections or interconnection wires. A capable routing is required to explore all the available approaches to streamline the performance as far as throughput, number of received packets, received flits, latency, energy and average power (Saini & Ahmed, 2015; Kourdy & Nouri, 2012). NoC configuration must be basic and short-way route is very considered for low inertness and power dispersal. another option to traditional on-chip correspondence coordinate with a uniform stackable multi-chip modules (MCM) in three-dimensional utilizing through silicon via (TSV). The change from 2D to 3D NoC is done by appropriating the tiles on to different layers of 3D NoC. (Paulo & Ababei, 2010) Explained outline of homogeneous framework on particular layers using heterogeneous floor plan (Sehgal, 2015). The router assignment-based plan approach is utilized for arrangement of Processing Elements (PE) on first layers and their limited association with the router is determined to the second layer. Application particular NoC plan with upgraded control utilization and least range managed rip up and reroute technique for coordinating streams and a router blending framework to streamline a given framework (Yan & Lin, 2011). NoC architecture gives a wide arrangement space including system topology, routing algorithms, and router design, where all impact framework execution to the impairment of different measures of system assets; along these lines the system design for such installed applications ought to be carefully chosen to meet the prerequisites (Matsutani, Koibuchi, & Amano, 2007). Such implanted applications frequently request tight outline imperatives regarding cost and performance, in this manner the silicon spending plan accessible for their on-chip mastermind structure should be unassuming as long as the required execution is met. System on-Chips (SoCs) have been concentrated to interface various processing cores on a solitary chip by acquainting a system structure comparable with that of parallel PCs (Dally & Towles, 2001) Other than NoCs, three-dimensional incorporated circuits (3D ICs) are another appealing answer for framework performance change by decreasing the interconnect length. (Beyne, 2006) However a noteworthy new worldview for proceeded with Moore's law incorporation is 3D chip stacks in light of an assortment of vertical interconnection techniques (Ye, Duan, Xu et al., 2009). 3Dintegration gives chances to cost diminishment and yield change in reconciliation of various advancements, for example, CMOS, DRAM and MEMS circuits through the capacity to actualize them over multiple die layers on a similar chip. It can likewise decrease shape factor in applications where estimate is basic, while powerful warmth dispersal and temperature control can be a test. To get the most preferred standpoint out of 3D chip stacks in multiprocessor systems, the correspondence configuration needs to help beneficial and high throughput vertical communication.

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