Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems

Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems

Ji Gu (University of New South Wales, Australia) and Hui Guo (University of New South Wales, Australia)
Copyright: © 2011 |Pages: 17
DOI: 10.4018/jhcr.2011100103
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Abstract

Instruction prefetching is an effective way to improve performance of the pipelined processors. However, existing instruction prefetching schemes increase performance with a significant energy sacrifice, making them unsuitable for embedded and ubiquitous systems where high performance and low energy consumption are all demanded. This paper proposes reducing energy overhead in instruction prefetching by using a simple hardware/software design and an efficient prefetching operation scheme. Two approaches are investigated: Decoded Loop Instruction Cache based Prefetching (DLICP) that is most effective for loop intensive applications, and the enhanced DLICP with the popular existing Next Line Prefetching (NLP) for applications of a moderate number of loops. The experimental results show that both DLICP and the enhanced DLICP deliver improved performance at a much reduced energy overhead.
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Instruction Prefetching Techniques

The proliferation of handheld, mobile and ubiquitous devices, has led to the research boom on embedded systems. Various design issues and approaches have been proposed. Bisdikian et al. (1998) present an experimental platform to research technologies and applications that enable ubiquitous, environment-aware, and low-cost computing of handheld devices in the wireless personal access networks. Medvidovic et al. (2003) developed a software-architecture-based scheme to support distributed computation on handheld devices. Several power management schemes at the hardware level have also been proposed to reduce power consumption in different mobile system components such as the displayer (Min & Cha, 2007), the graphic processing unit (Nam, Lee, Kim, Lee, & Yoo, 2008).

Our proposal in this paper is an energy-efficient instruction prefetching scheme for embedded processors that can be used in the mobile/handheld devices for high system performance and low energy consumption. This section reviews some existing instruction prefetching methods for cache performance optimization.

Existing instruction prefetching techniques can be classified as software based prefetching and hardware based prefetching. Software prefetching schemes (Gornish, Granston, & Veidenbaum, 1990; Luk & Mowry, 1998; Cristal et al., 2005) rely on the compiler to insert prefetch instructions into the program code before the application is executed, which requires a known memory access behavior and a dedicated compiler.

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