SecCMP: Enhancing Critical Secrets Protection in Chip-Multiprocessors

SecCMP: Enhancing Critical Secrets Protection in Chip-Multiprocessors

Li Yang (University of Tennessee at Chattanooga, USA), Lu Peng (Louisiana State University, USA) and Balachandran Ramadass (Louisiana State University, USA)
Copyright: © 2008 |Pages: 13
DOI: 10.4018/jisp.2008100103
OnDemand PDF Download:
Available
$37.50
Current Special Offers
No Current Special Offers
TOTAL SAVINGS: $37.50

Abstract

Security has been considered as an important issue in processor design. Most of the existing designs of security handling assume the chip as a single secure unit. However, such assumption is vulnerable to exposure resulted from a central failure point. In this article, we propose a secure Chip-Multiprocessor architecture (SecCMP) to handle security related problems such as key protection and core authentication in multi-core systems. Matching the nature of multi-core systems, a distributed threshold secret sharing scheme is employed to protect critical secrets. A critical secret (e.g., encryption key) is divided into multiple shares and distributed among multiple cores instead of being kept a single copy in one core that is sensitive to exposure. The proposed SecCMP can not only enhance the security and fault-tolerance in secret protection but also support core authentication. SecCMP is designed to be an efficient and secure architecture for CMPs.

Complete Article List

Search this Journal:
Reset
Open Access Articles
Volume 16: 4 Issues (2022): 1 Released, 3 Forthcoming
Volume 15: 4 Issues (2021): 3 Released, 1 Forthcoming
Volume 14: 4 Issues (2020)
Volume 13: 4 Issues (2019)
Volume 12: 4 Issues (2018)
Volume 11: 4 Issues (2017)
Volume 10: 4 Issues (2016)
Volume 9: 4 Issues (2015)
Volume 8: 4 Issues (2014)
Volume 7: 4 Issues (2013)
Volume 6: 4 Issues (2012)
Volume 5: 4 Issues (2011)
Volume 4: 4 Issues (2010)
Volume 3: 4 Issues (2009)
Volume 2: 4 Issues (2008)
Volume 1: 4 Issues (2007)
View Complete Journal Contents Listing