Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

Alessandro Strano (University of Ferrara, Italy), Carles Hernández (Universidad Politécnica de Valencia, Spain), Federico Silla (Universidad Politécnica de Valencia, Spain) and Davide Bertozzi (University of Ferrara, Italy)
DOI: 10.4018/jertcs.2011100101
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Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies are the root causes for this. This article addresses the challenge of designing a process variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. A suitable delayed replica of the transmitter clock is then selected for safe sampling of misaligned data. The manuscript proves robustness of the link in isolation with respect to a detector-less link, but also assesses integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.
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Many recent works analyze the impact of process variations on the performance of integrated circuits, providing data on how parameter variations impact the maximum design frequency (Bowman et al., 2002) or variability models that characterize variations in microarchitecture (Sarangi et al., 2008; Bonesi et al., 2008). However, these studies do not consider the implications of variations in the interconnect infrastructure. Although (Nicopoulos et al., 2010) is a step forward in this direction, this study neglects the impact of manufacturing deviations on NoC links. Unfortunately, this impact is not negligible (Mondal et al., 2007; Hernández et al., 2010; Hassan et al., 2009). On one hand, although there are examples of repeater-less NoC self-calibrating links (Jose et al., 2005), they typically undergo repeater insertion. Therefore, they suffer from Lgate variations and dopant fluctuations in the transistors building up repeater stages, and also suffer from the variability introduced by the chemical metal planarization process (Mondal et al., 2007).

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