Signature Restoration for Enhancing Robustness of FPGA IP Designs

Signature Restoration for Enhancing Robustness of FPGA IP Designs

Jing Long (College of Computer Science and Electronic Engineering, Hunan University, Changsha, China), Dafang Zhang (College of Computer Science and Electronic Engineering, Hunan University, Changsha, China), Wei Liang (College of Computer Science and Engineering, Hunan University of Science and Technology, Xiangtan, China) and Xia'an Bi (College of Mathematics and Computer Science, Hunan Normal University, Changsha, China)
Copyright: © 2015 |Pages: 16
DOI: 10.4018/IJISP.2015070103


Many watermarking techniques for intellectual property (IP) protection are not resilient to tampering or removal attacks, especially for field programmable gate array (FPGA)-based IP cores. If attacked, the damaged watermarks cannot provide sufficient evidence in front of a court. To address this issue, the authors present a signature restoration scheme. The thought of secret sharing is introduced to share the signature into small watermarks. These watermarks are encoded with Reed-Solomon (RS) codes and embedded into unused lookup tables (LUTs) of used slices. Unlike most of existing techniques, the proposed scheme can restore the signature only by extracting parts of watermarks. So, it is tolerant to some damaged watermarks caused by removal attacks. The experiments show that the proposed scheme incurs no extra hardware resource and timing overhead. The robustness against attacks is much better by comparing to other schemes.
Article Preview


The advance in silicon technology allows more capabilities to be fitted on a single chip. All these facts lead to substantial changes in current design methodologies, directly to reduce design cycle and cost, finally shorten the time to market. In recent years, field programmable gate array (FPGA) plays an increasingly important role in integrated circuit (IC) design due to its reprogramming feature (Chakraborty & Bhunia, 2009; Dutt & Li, 2009). It offers a flexible solution for the implementation of valuable designs. So, the integration of multiple predesigned components, namely intellectual property (IP) on a FPGA chip, attracts more concerns. In the view of FPGA system integrators, the reuse of predesigned IP is prevalent and effective to integrate multiple IP cores into a single FPGA chip. It brings many advantages, but the integration of IPs in a system makes them vulnerable to be attacked (Cui, Chang & Tahar, 2008; Abdel-Hamid, Tahar, & Abboulhamid, 2005; Cocchi, Baukus & Chow, 2014). The vicious party may misappropriate these IP cores as their own, forge or sell them to acquire illegal benefits. Consequently, IP protection for FPGA design is an inevitable security issue in development of integrated circuits.

The virtual socket interface alliance classifies IP protection solutions into three categories, deterrent, protection and detection (VSI Alliance, 2001). The deterrent techniques mean to deter IP privacy by using legal actions, e.g. patenting and contract, without any physical protection to IP core itself. Conversely, the protection techniques prevent IP core from misappropriation by using active protective mechanism, such as encryption, license and watermark. These are effective to trace the use of IP core and identify its legality. Watermarking is a prevailing protection technique. It is cheaper and more effective than patenting or encryption. IP watermarking usually hosts a signature into IP design to declare the copyright or tracing infringement (Qu, 2002). Once privacy is suspected, legal IP owner can apply to verify the suspected IP design. Successful detection of a valid signature proves the ownership of IP core.

The content of IP core is different with that in media industry. It is developed at several abstract levels of design by means of complicated design tools, such as Xilinx ISE. The watermarks need to satisfy various design constraints at each abstract level. Many watermarking schemes for FPGA IPs are realized by altering a design itself or adding redundancy into a design (Kahng, Lach, & Mangione-Smith, 2001; Saha & Sur-Kolay 2010; Marchand, Bossuet & Jung, 2014; Zhang & Chang, 2014; Chang & Zhang, 2014). They involve several levels of design abstraction, e.g., FSM at behavioral level and layout at physical level. Watermarks at different levels can be implemented through many ways, but the goal is to make the IP core unique with high credibility. At higher levels, the watermarks need to survive the optimization so that the lower levels can be also protected. Otherwise, it is hard to provide sufficient evidence in front of a court. A different case occurs at low design level. The result after watermark embedding is predicable. But these watermarks are always easily suffered from tampering or removal attacks. Existing techniques have introduced some security mechanisms in watermarking for better robustness, e.g., encryption (DES, AES, etc.), error correction codes. But it is not enough to recover a signature if any watermark is removed by vicious attackers.

This work is organized as follows. Section 2 provides an overview of related work for FPGA IP Watermarking. Section 3 describes the proposed scheme. Section 4 presents experimental results. In Section 5, the paper is summarized.

Complete Article List

Search this Journal:
Open Access Articles
Volume 14: 4 Issues (2020): 2 Released, 2 Forthcoming
Volume 13: 4 Issues (2019)
Volume 12: 4 Issues (2018)
Volume 11: 4 Issues (2017)
Volume 10: 4 Issues (2016)
Volume 9: 4 Issues (2015)
Volume 8: 4 Issues (2014)
Volume 7: 4 Issues (2013)
Volume 6: 4 Issues (2012)
Volume 5: 4 Issues (2011)
Volume 4: 4 Issues (2010)
Volume 3: 4 Issues (2009)
Volume 2: 4 Issues (2008)
Volume 1: 4 Issues (2007)
View Complete Journal Contents Listing