A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs

Introduction

Nowadays, heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) are the de-facto standard for embedded system design (Wolf et al., 2008) where general purpose processors are connected also with digital signal processors and hardware accelerators to speed up the applications. Platform-based design (Sangiovanni-Vincentelli & Martin, 2001) has been established to tackle the design complexity by performing a progressive refinement of the architecture, but, even when MPSoCs have already been designed, different issues are still open to meet the design requirements, especially when the customization with hardware accelerators needs to be investigated.

In the platform-based design, the initial application is first decomposed in chunks of instructions (called tasks) and usually represented as functions, which may be potentially executed in parallel. Then, these tasks have to be assigned to the architecture resources (mapping) devoted to their execution, so that all the architectural constraints are satisfied. In this work, we focus on the latter part of the problem, discussing how, after an application has been decomposed, different mapping solutions can be evaluated and compared, especially when the execution of the application is data-dependent (Gries, 2004). In these cases, the designers usually need to interface with simulators to characterize the systems and assess the performance of the application.

In such a scenario, the Y-chart design methodology (Pimentel et al., 2006) (shown in Figure 1) is one of the most popular approaches for the design space exploration devoted to the system-level synthesis of MPSoCs: starting from an application and an architectural platform which parameters can be further customized, the tasks are mapped to the processing elements; a performance analysis of the identified solution is then carried out and, finally, the obtained metrics’ values (e.g., performance, power consumption, area) are analyzed to give a feedback for improving the solution (i.e., the architecture, the application and the mapping). Such process is then iterated until the solution meets the requirements imposed by the designer. For these reasons, automating this process is a crucial step for reducing the time required to generate high-quality solutions.

Figure 1.

Different phases of the design space exploration

Besides analytical approaches (Agosta et al., 2007, Ferrandi et al., 2010), based on worst case execution time estimation and static scheduling, the designer may require additional information by means of simulations, at different abstraction levels, especially when the actual platform is not fully implemented. These simulators can consider either SystemC performance models (e.g., Kempf et al., 2005) or slower but more accurate ISS-based Instruction Set Simulators (ISSs) (e.g., Qin & Malik, 2003, Beltrame et al., 2006, Beltrame et al., 2009, Synopsys, 2012). In this paper, we focus on the case where the designer desires to perform a simulation of the complete system (i.e., mapped application running on the top of the target architecture) to enable an accurate tuning of the design parameters, both architectural and application’s ones. In this scenario, if the exploration of architectural parameters and the application optimization through code transformations have been already addressed by several approaches (Agosta et al., 2007, Beltrame et al., 2010, Mariani et al., 2012), the exploration of mapping solutions presents several issues, especially in the case of hardware accelerators, that have not been fully automated yet. Indeed, in most of the cases, the generation of the models for the hardware accelerators and their interfacing with the rest of the application is manually performed, preventing the possibility of automating the exploration.