System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor

System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor

Di Wu, Johan Eilert, Rizwan Asghar, Dake Liu, Anders Nilsson, Eric Tell, Eric Alfredsson
DOI: 10.4018/jertcs.2010070103
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The evolution of third generation mobile communications toward high-speed packet access and long-term evolution is ongoing and will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier de-mapping. The throughput and latency requirements of a Category four User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ, which brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.
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3GPP Long-Term Evolution (LTE) is the forthcoming radio access technology which incorporates Orthogonal Frequency Division Multiple Access (OFDMA) as the multiple-access scheme in downlink. Compared to existing Code Division Multiple Access (CDMA) based technologies (e.g., WCDMA, CDMA2000 and TD-SCDMA), LTE is more optimized for data service and achieves higher spectral efficiency. Furthermore, LTE brings the scenario of Frequency Division Duplexing (FDD) and Time Division Duplexing (TDD). Hence it is very likely that LTE will be deployed to replace existing WCDMA, CDMA2000 and TD-SCDMA in the future for the ever-increasing data traffic.

As the standardization of 3GPP LTE is still ongoing, the features defined will keep evolving along with the time as what has happened with 3G standards. Therefore, it is essential to design a scalable platform which supports the change of standard specifications without the redesign of hardware. The downlink receiver chain of an LTE modem is depicted in Figure 1.

Figure 1.

Functional flow of an LTE Modem (physical layer only)


There are a number of design challenges for LTE such as frequency synchronization, channel estimation, Multiple-Input Multiple-Output (MIMO) detection, Hybrid Automatic Repeat ReQuest (H-ARQ) and high-throughput forward error correction (FEC) decoding. Meanwhile, in order to cover legacy standards (e.g., WCDMA and DVB) and other new standards (e.g., WiMAX), either multiple Application Specific Integrated Circuits (ASIC) modems (one for each standard) have to be integrated into a chip or a programmable hardware which can handle multiple standards (Nilsson, Tell, & Liu, 2009) has to be used. The first solution not only consumes a significant amount of hardware, it also requires more integration work. The second solution is called software-defined radio (SDR) which exploits the similarity among different signal processing tasks to allow hardware multiplexing. SDR with an efficient architecture only consumes slightly more hardware while being able to support multiple standards, compared to single-standard ASIC solutions.

In Berkmann et al. (2008), implementation issues of an LTE modem is presented with insight to both the algorithms and their implementation cost estimation. However, to the best knowledge of the authors, detailed information of Software Defined Radio (SDR) based LTE modems are not yet available in literatures. In this paper:

  • The architecture and implementation results of an LTE category 4 modem based on a novel programmable baseband processor, LeoCore of Coresonic (Nilsson, Tell, & Liu, 2009), is presented, which is the first SDR based LTE modem presented in the literature with architectural and performance information.

  • The implementation of a MIMO detector that supports both MMSE and a novel low-complexity close-Maximum-Likelihood (close-ML) MIMO detection method is presented.

  • The implementation of a parameterized parallel Radix-2 Turbo decoder that supports all block sizes is presented.

  • The link-level performance of the complete LTE receiver is presented with various signal distortions taken into consideration. The degradation due to errors introduced in different processing stages is presented in the simulation result.


Overview Of 3Gpp-Lte Features

The LTE modem presented in this paper meets the physical layer requirements listed in Table 1.

Table 1.
Supported LTE UE categories. 3GPP (2008)
UE Category (CAT)1234
Supported Bandwidth1,4,3,5,10,15,20 MHz
Antenna ConfigurationsUp to 2x2 SM and SFBC
Num of Layers for SM12
Max num of Soft-bits250368123724812372481827072
DL peak rate (Mbit/s)1050100150
UL peak rate (Mbit/s)5255050
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