Using Machine Learning Techniques for Performance Prediction on Multi-Cores

Introduction

Multi-core has become the dominant processor architecture at present. Majority of the computing systems are based on multi-core processors, which include both the desktops as well as servers. In future the number of cores on a single processor chip is going to increase with the upcoming generations of processors. Most of the recent multi-core processors have last level caches, which are shared among the cores (Intel Corporation; Kongetira, Aingaran, & Olukotun, 2005; Golla, 2006). Programs co-running on the cores of multi-core processors also share other resources such as hardware prefetch unit, Front Side Bus (FSB) and memory controller along with last level caches. Along with the growth in number of cores per chip with the generations of processors, future multi-core based systems are poised to witness increased degree of sharing of the resources.

The interference between programs co-running on the cores sharing the resources causes degradation in the performance of systems based on multi-core processors. For example a process on one core may cause the eviction of data belonging to process on the other core, with which it shares the cache space. Such interference between co-running programs due to use of shared cache space can cause the performance of simultaneous running processes to get affected by each other. We measured the performance of some of programs from SPEC cpu2006 benchmark suite (SPEC, 2006) on our Intel quad-core Xeon X5482 processor based experimental platform (described in section named EXPERIMENTAL PLATFORMS) for their solo-run as well as concurrent-run. The values of solo-run and concurrent-run performance for those programs in terms of cycles per instruction (CPI) are mentioned in Table 1.