Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization

1. Introduction

The art of the physical design is referred to as floor planning. Several systems have used the Very Large Scale Integration (VLSI) design approach to open up new possibilities for high-performance computing, telecommunications, and ordinary electronic devices (e.g., entertainment). Moore's Law states that as VLSI technology has advanced, the number of manufactured devices in a single integrated circuit has steadily increased. To ensure quality, stability, and extensibility, it is more important to regulate the design process due to the rise in complexity, which includes significant bookkeeping and administrative responsibilities. With recent technological advancements, system design has expanded significantly, as well as the count of transistors on a chip has surpassed the range of possible combinations. As a consequence, Physical Design has become increasingly essential throughout the VLSI designing phase (Zhang et al. 2020; Vipin 2019; Singh and Baghel 2021). Floor planning seems to be the fundamental step in the Physical Design Flow process. This specifies the positions and size of modules upon the chip to maximize the chip's surface area. One key limitation to considering the locations of the modules is that there's no overlapping between two modules (Sivaranjani and Senthil Kumar 2015; Shunmugathammal et al. 2020a; Srinivasan and Venkatesan 2021; Prakash and Lal 2021). To deal with the rising complexity of architecture, hierarchical and IP-based components are utilized, making floor planning throughout the VLSI design cycle is increasingly realistic. Researchers have recently discovered the benefits of VLSI floor planning (Vipin 2019; Lin et al. 2021a; Mohapatra et al. 2020), particularly comprising a large number of chips. The architecture that must be recognized has been put together in floor planning, and specific space should indeed be allocated with different satisfactory limits to bring things close together, thereby reducing the dead space and cost incurred (Singh and Baghel 2021; Sivaranjani and Senthil Kumar 2015). The dynamics of the model is reduced. In the integrated circuit design floor planning is the major step (Andrukhiv et al. 2020; Singhet al. 2021).