This article describes how, in recent years, with the development of microelectronics, implantable electronic devices have been playing a significant role in modem medicine. Examples of such electronic implant devices are, for instance, retinal prosthesis and brain implants. It brings great challenges in low power radio frequency (RF) and analog designs. This article presents a low power Gaussian frequency shift keying (GFSK) demodulator designed for Medical Implant Communications Service (MICS) band Receiver. This demodulator utilizes a novel structure that a wide IF range can be handled and presents the smallest Δf/f ratio in any published GFSK demodulators. In theory the demodulation method can be applied to any RF frequency. The demodulator draws 550uA from a 1 V power supply. A maximum data rate of 400 Kbits/s can be achieved within the 300 KHz channel bandwidth defined by MICS. A simulated signal-to-noise ratio (SNR) of 15.2dB at AWGN channel is obtained to achieve 10-3 bit error rate (BER). This demodulator is fabricated on 65-nm CMOS and occupies 0.12mm2 silicon area.
TopIntroduction
The MICS band is an ultra-low power, unlicensed mobile radio service for implanted medical device. Ten 300 KHz channels are allocated at 402-405 MHz frequency band (“FCC Rules and Regulations,” 2002). Implanted wireless device has a requirement of high reliability and ultra-low power consumption. Recent CMOS technology has enabled the design of reliable, low power and cost effective wireless transceiver. This demodulator is designed on 65nm technology under 1 V supply. It intends to be used for the epi-retinal prosthesis (Bionic Eye) to demodulate data for a 32x32 electrode array. In order to support these 1024 electrodes, a data rate more than 300 Kbps is required to make fully functional. Achieving high date rate and low power consumption from this limited 300 KHz bandwidth are challenges in the design of such system. So far, amplitude shift keying (ASK) and binary shift keying (BFSK) have been widely used in biomedical implants (Ghovanloo, Beach, Wise, & Najafi, 2002; Ghovanloo & Najafi, 2003). However, these two methods are not bandwidth efficient. This paper presents a demodulator that can work for both continuous phase BFSK and GFSK modulation schemes. Using GFSK, a data rate up to 400 Kbit/s is achieved within the given 300 KHz bandwidth. This demodulator is also immune to a frequency offset up to 4 MHz. A BER of 10-3 is obtained at SNR of 15.2 dB at the input.
Figure 1. Block diagram of receiver with the proposed GFSK demodulator
TopDemodulator Architecture
The Architecture of the RF receiver is shown in Figure 1. The RF frequency is down converted from MICS band, 402-405MHz to around 5 MHz. A channel-select filter is used to reject the image and select the desired channel. Then the limiter amplifies the IF signal to rail-to-rail swing. Block diagram of proposed GFSK demodulator is shown in the dashed box of the figure. It consists of four blocks: delay line, delay flip-flop (DFF), gm-c low pass filter, and decision-making circuit. The delay element delays the IF input by approximate half the bit period. Then the DFF uses the delayed signal as the clock to sample the original signal. So the frequency information of GFSK signal is mapped into the density and width of the pulse train. After that, the low-pass filter converts the frequency information into voltage level difference. The voltage level after low-pass filter (LPF) may experience variation, as it can be affected by the frequency offset, pulse width variation, and process variation. The decision-making circuit is at the final stage to make a decision on the specific input.
Compared with conventional phase-quantization-based GFSK demodulator (Han & Zheng, 2009) and delay-line based BFSK demodulator, the proposed demodulator can tolerate much larger frequency offset. In other words, it is capable of working at a wider frequency range. Figure 2 shows the principle how this demodulator works at different frequencies. A BFSK signal with bit sequence starting with “010” is used as IF input. Two frequency tones f1 and f2 are used to present logic “1” and “0” respectively. Frequency deviation is Δf, where Δf = f2 - f1. From time t0 to t1, IF signal is sampled by its own delayed signal with same frequency f2, therefore the DFF produces a pulse train with equal pulse width at Q output. Then between time t1 and t2, frequency of original signal, f1, is smaller than that of the delayed signal, f2, so the pulse width at Q output of DFF is drifting. Since t2, both original signal and delayed signal are represented by frequency f1, the output of Q maintain the same width until t2 when the bit transition of original signal occurs. From t3 to t4, the two signals again are having different frequencies. But this time IF signal is sampled at a lower frequency f1. This is a reversed process of the pulse width drift happened between t0 and t1.It can be concluded that output pulse width is fixed at the center of each bit period, pulse width drift occurs around bit transition. Thus, frequency information of FSK signal is contained in the pulse train. When GFSK signal is applied, a similar output would be resulted except that the width of pulse changes continuously. Simulation result with GFSK input will be shown in the last section.
Figure 2. Operation concept of self-sampling