A Unified Analog Synthesis Approach Considering Parasitic Effects and Process Variations

A Unified Analog Synthesis Approach Considering Parasitic Effects and Process Variations

Yen-Lung Chen (National Central University, China) and Chien-Nan Jimmy Liu (National Central University, China)
DOI: 10.4018/978-1-4666-6627-6.ch003
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Abstract

Manually designing the analog/RF and power circuits to meet requirements is often considered a difficult task that takes a lot of time. Several automatic circuit-sizing approaches have been proposed for typical analog circuits to solve this bottleneck, but the performance and yield is unexpected if the non-ideal effects are not considered. In this chapter, an equation-based automatic synthesis approach for analog circuits is proposed. The layout-induced parasitic effects and process variations are also considered simultaneously to guarantee the circuit performance after manufacturing. As shown in the experimental results, the proposed approach successfully solves the unreachable specification in previous work and keeps the performance and yield of the generated circuit even in post-layout simulations. The incurred hardware overhead is also reduced by using the proposed unified approach, which demonstrates the feasibility and efficiency of this approach.
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Introduction

Typical analog design procedure often requires simultaneous optimization between different specifications. Manually designing the circuits to meet the requirements is often considered as a difficult task, which often takes a lot of time. While the device size is continuously shrinking in deep submicron process, more non-ideal effects also bring more challenges to sensitive analog circuits. Therefore, various design automation approaches have been proposed for analog circuits to solve this design bottleneck (Rutenbar, Gielen, & Roychowdhury, 2007). Besides the benefit of fast design procedure, good design automation algorithms also provide proper considerations between multiple objectives.

Analog design automation has two important steps: circuit sizing and layout generation. In the literature, the automatic circuit sizing approaches can be roughly classified into three categories. Knowledge-based optimization (Mahattanakul & Chutichatuporn, 2005) generalizes designers’ experience and obtains a design solution based on some pre-defined design flows and database. Although this method is quite fast, the optimality of the solution cannot be guaranteed. The general solution for the sizing problem is adopting circuit simulators in the sizing iterations until finding the relatively better design (Lin, Sue, Shyu, & Chang, 2009). This approach can obtain more accurate results, but the required computation time is relatively longer among various kinds of approaches. Equation-based approaches use the mathematical solvers to solve the circuit equations and obtain the global optimal solutions, such as the geometric programming (GP) based approaches in (Hershenson, Boyd, & Lee, 2001). These approaches are extremely fast, but the accuracy is often limited due to the simplified circuit equations.

After the device parameters are determined, the next design step is to generate the corresponding layout. In the literature, layout automation techniques for analog circuits are also a popular research direction (Weng, Chen, Chen, Pan, Chen, & Chen, 2011). In advance technology, layout effects have large impacts on circuit performance and design yield. Due to the parasitic effects, the performance between pre-layout simulation and post-layout simulation might be quite different, which may make the circuit performance fail to meet the specifications after layout. In such cases, designers have to redesign the circuits and layouts, which is a time-consuming loop. In conventional design flow, those parasitic effects can only be estimated after layout completion. Therefore, several sizing-layout iterations are still required in previous layout-aware synthesis approaches (Ranjan, Verhaegen, Agarwal, Sampath, Vemuri, & Gielen, 2004; Agatwal & Vemuri, 2005; R. Castro-Lópe, Guerra, Roca, Fernández, 2008). Due to the tedious post-layout simulations, the sizing-layout iterations greatly slow down the whole synthesis procedures.

After the layout is completed, the next step is to fabricate the chip. However, because the process variation effects are often not considered, traditional optimization algorithms typically push the system performance to some corners that are vulnerable to parametric variations (Graeb, 2007). In advance process with significant process variations, robust analog circuit optimization becomes increasingly important. In the literature, many remarkable techniques are proposed based on simulation-based synthesis approaches (McConaghy & Gielen, 2009; Liu, Fernández, & Gielen, 2011). After the device sizes are obtained in each iteration, the design yield is also evaluated while simulating the circuit performance. Therefore, in the following optimization process, the design yield can also be treated as one target to be optimized together. Although these approaches have accurate results, they often require much more computation time due to the tedious simulations in the optimization process. If the design yield should be evaluated also in each optimization iteration, the required computation time will be further increased. As reported in previous studies, several hours are often required to optimize a typical-sized circuit.

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