An Optimized FPGA Architecture for Sleep Level Categorization Using Fuzzed Utilized Machine Learning Approach

Introduction

Neurodegenerative diseases affect millions of people around the world. Electrical brain stimulation has shown to be an effective, low-side-effect option for treating neurodegenerative disorders compared with many conventional pharmaceutical methods (J. Horne & M. McGrath, 19841) In the case of Alzheimer’s disease (AD), epidemiological studies have discovered a correlation between the development of AD and stages of sleep, which is dominated by cycles of REM (rapid eye movement) that disrupts memory consolidation and NREM (non-REM) sleep that promotes memory consolidation(A. Bianchetti, A et al ., 1995). Studies found that stimulating the lateral hypothalamus at the peaks of θ oscillation (5-10 Hz) significantly increases the chances of suppressing REM sleep (A. R. Adamantidis, et al., 2007). This motivates the development of a sleep stage classifier with high accuracy and low detection latency (< 1 ms) in order to deliver such timely stimuli by responsive stimulation.

Several software-based algorithms have already been developed for classifying sleep stages(V. Bajaj & R. B. Pachori,2013; F. Ebrahimi et al.,2008). Although these algorithms often achieve high detection accuracy, they require significant amounts of computational power, which prevents their implementation on low-power, wearable devices. Additionally, sending the recorded signal from a data acquisition module to a computer creates long delays that prevent responsive stimulation for REM suppression. These shortcomings motivate the design for a digital implementation on a FPGA-controlled wearable device capable of neural recording, real-time REM sleep stage detection, and close-loop brain stimulation.

Recently, several hardware based REM detection algorithms have been developed(A. Chemparathy, et al.,2014; M. Fajar &W. Jatmiko et al., 2012; W. Karlen, C. Mattiussi, & D. Floreano, 2007) . In these algorithms, multiple bio-signals, such as electroencephalogram (hippocampus and cortex EEG) and electromyogram (EMG) signals in (A. Chemparathy, et al.,2014) are first bandpass-filtered and averaged .Existing REM detection algorithm(A. Chemparathy, et al.,2014). cortex EEG (0-4 Hz), and EMG oscillations (100-200 Hz) are most prevalent in REM, NREM and AWAKE stages, respectively. Although these algorithms have been shown to achieve high REM classification accuracy with low detection latency, their high power and resource consumption make them unsuitable for implementing on low-power (< 1 mW) wearable devices. In this paper, a multichannel FIR filter is implemented through time division multiplexing mechanism using single multiplier and adder irrespective of number of taps and number of channels by applying the principle of resource sharing in order to optimize the area.

After preprocessing then the signal is classified based on the reference data with the use of self-regulated machine learning and fuzzy deduction schemes which involves averaging and thresholding process. Further, the signals are categorized into completely awake level, partially awake level, and sleep level using fuzzy if-then rules. Automatic sleep stage categorization employing heart rate variability is performed with a long short-term memory architecture in order to model the long-term cardiac sleep architectural details (Mustafa Radha et al., 2019). Automated sleep stage detection algorithms are useful to analyze the PSG (polysomno-graphic) data quickly. Feature oriented categorization algorithms and approaches are utilized to improve the performance of sleep stage detection system (Alexandra-Maria Tăutan et al., 2020). Automated sleep stage categorization approach utilizing convolutional neural network and fine-grained segment incorporates multiple channel EEG signal segments which are processed using softmax classifier to provide the desired stage detection automatically (Zhihong Cui et al., 2002)

The rest of the paper is organized as follows: Section II outlines algorithmic design specifications and provides a resource utilization analysis. Section III highlights innovations in the optimized implementation that significantly reduces FPGA resource consumption. Section IV compares the performance of the new implementation with the current state of the art implementations.