CNTFET-Based Ternary Logic Gates: Design and Analysis Approach

CNTFET-Based Ternary Logic Gates: Design and Analysis Approach

Suman Rani (I.K.G. Punjab Technical University Jalandhar, Punjab, India & Baba Farid College of Engineering and Technology, Bathinda, India.) and Balwinder Singh (ACS Division, Centre for Development of Advanced Computing, Mohali, India)
DOI: 10.4018/978-1-7998-1393-4.ch005

Abstract

In the recent digital designs, there are certain circumstances where energy efficiency and ease is required, and in such situations, ternary logic (or three-valued logic) is favored. Ternary logic is an auspicious supernumerary to the conventional binary (0, 1) logic design techniques as this one is possible to attain straightforwardness and energy efficiency. This chapter deals with the comparative analysis of CMOS and CNTFET-based ternary inverter and universal gates design. The simulation result is analyzed and validated with a Hailey simulation program with integrated circuit (HSPICE) simulations. The average delay and power consumption in CNTFET-based ternary inverter have been reduced by approximately 90.3% and 48.8% respectively, as compared to CMOS-based ternary inverter design. Likewise, delay is reduced by 50% and power gets 99% reduction in ternary CNTFET NAND gate as compared to CMOS-based ternary NAND gat. It is concluded that CNFETs are faster and consume less power compared to CMOS technology.
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1. Introduction

Simplicity and energy efficiency are one of the most significant features of up-to-date electronics systems intended for high-performance handy applications. Usually, Logics and algorithms in digital computations are based on the two-valued code, that is, high or low, or yes or no or (0 or 1). On the other hand, in few conditions, we exercise a state in which it is problematic otherwise needless to choose right or false. For illustration, in a transient state (changes from 0 to 1 or 1 to 0), it is difficult to resolve whether the value of the state is 0 or 1. Then ternary logic (three-valued logic) can be used, as an alternative of binary logic (two-valued logic), in which the third value i.e truth is familiarized to signify an indefinite state separately since true and false. Henceforth multivalued Logic substitutes the conventional Boolean characterization of the variable by many values for example Ternary logic (Mukaidono, 1986, p.179).

Key Terms in this Chapter

Carbon Nanotube Field-Effect Transistor: A carbon nanotube field-effect transistor is referred to as FET. It utilizes one or multiple CNTs as a channel between the source and drain terminal.

Carbon Nanotube: CNTs, the allotropes of carbon that belong to the fullerenes family, are the Nano-scaled tube formed by the rolled sheets of graphite.

Multi-Valued Logic Design: To enhance the performance of CMOS technologies, MVL modules have been inserted in binary logic ICs. Based on MOS technology, MVL circuits further categories as current-mode MVL circuits and another one is voltage-mode MVL circuits.

Ternary CMOS: A ternary CMOS is a transistor that uses ternary logic (three possible values) as an alternative of the more widely held binary system (“Base 2”) in its calculations.

Delay: Is the length of time that starts when the input to a logic gate becomes stable and valid to change to the time that the output of that logic gate is stable and valid to change.

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