Co-Modeling of Embedded Networks Using SystemC and SDL: From Theory to Practice

Co-Modeling of Embedded Networks Using SystemC and SDL: From Theory to Practice

Valentin Olenev (St. Petersburg State University of Aerospace Instrumentation, Russia), Irina Lavrovskaya (St. Petersburg State University of Aerospace Instrumentation, Russia), Pavel Morozkin (St. Petersburg State University of Aerospace Instrumentation, Russia), Alexey Rabin (St. Petersburg State University of Aerospace Instrumentation, Russia), Sergey Balandin (Open Innovations Association FRUCT, Finland) and Michel Gillet (Nokia Research Center, Finland)
DOI: 10.4018/978-1-4666-6034-2.ch009
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Abstract

This chapter gives an overview of a modeling application in the general embedded systems design flow and presents two general approaches for the embedded networks simulation: network modeling and protocol stack modeling. The authors select two widely used modeling languages, which are SDL and SystemC. The analysis shows that both languages have a number of advantages that could be combined by the joint use of SystemC and SDL. Thus, the authors propose an approach for the SystemC and SDL co-modeling. This approach can be used in practice to perform protocol stack simulation as well as simulation of network operation. Therefore, the authors give examples of co-modeling practical applications.
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Embedded Systems Design Flow

An embedded system is a specific combination of computer hardware and software which is specifically designed to perform a particular function (or a range of functions) of a larger system. It usually has strict real-time computational, size and energy restrictions (Heath, 2003), (Barr, 2006), (Kamal, 2008).

There are many implementation steps needed to build an embedded system, and each step is a set of complex actions. Performance modeling helps to understand and establish the major characteristics of the future product. The result of the functional modeling is a specification of the product’s functional behavior. During the design and synthesis step the developers implement the specified mechanisms in details and check them. Validation and verification step ensure that the final implementation behaves in a strong accordance to the specification. All these activities operate on models and not on the real physical object. The reasons for using a model are that, firstly the real product is not available on a development stage, and secondly it is much cheaper to test the specification of a model that on a real device prototype. (Jantsch, 2004).

The embedded systems design encounters a number of difficulties caused by increasing complexity of projects, increasing requirements to products reliability, power consumption and demand to speed-up the project design phase. So the modern approach to the system design implies the parallel execution of some design tasks. It is illustrated by Figure 1 and includes the following stages:

Figure 1.

General design flow

  • Conceptual System Design: The primary goal of this stage is the main system description, analysis of the system mechanisms and development of the first specification draft;

  • Specification: This stage is targeted to get the final version of the system specification and the system model in a high-level language (usually in С/С++, SDL);

  • Logical (Architectural) Design: Includes translation of the executable project specification to the register level (in Verilog/VHDL) and further at the gate level;

  • Project Verification: Verification of the design decisions on conformity to the specification and other requirements;

  • Physical Design: This stage begins from the selection of technological and library basis and it is completed when everything is ready for the final product production.

The main purpose of Figure 1 is to show the modeling role in the general design flow. Also this picture proves that modeling could be used on every design stage (Olenev 3, 2009).

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