CPU Architecture

CPU Architecture

Copyright: © 2017 |Pages: 18
DOI: 10.4018/978-1-68318-000-5.ch002

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Von Neumann Architecture

The philosophy of this architecture is based upon the fact that instructions and data share the same memory as shown in Figure 1. Since the data bus is 8-bit wide, an instruction consisting of an opcode1 (operation code) and one or more operands2 obviously occupies more than one byte in memory. Consequently, an instruction occupying 3 bytes of storage elapses 3 cycles to be read plus additional cycles to be executed. This slows down the CPU tremendously and limits its operating bandwidth. Traditionally, microcontroller manufacturers used the Von Neumann architecture. In order to further understand this architecture, let us consider the Freescale 68HC11 microcontroller instruction stored at memory address 0x0100:

This instruction occupies 3 bytes of memory: the opcode (0xB6) followed by the high-order and low-order bytes of the address (0x12 and 0x34). This implies that the CPU requires 3 cycles to read the instruction plus one additional cycle to execute it; a total of 4 cycles. This is quite a waste of time and resources from a Harvard machine point of view whose basic philosophy is to read the instruction in one cycle.

Figure 1.

Von Neumann basic architecture

Table 1 illustrates the cycle-by-cycle execution of the instruction. In the first cycle, the CPU puts the instruction’s address 0x0100 on the address bus to read its opcode 0xB6. Then the processor reads the instruction’s operand (memory address 0x1234) in 2 additional cycles. Subsequently, the CPU puts address 0x1234 on the address bus in order to read its contents. In a microprocessor system, instructions occupy non-volatile memories of the ROM (Read Only Memory) type whereas variables reside in alterable memories of the RWM (Read Write Memory) type. Therefore, in a Von Neumann machine, memory is a mixture of ROM for instructions and lookup tables, and RAM3 (modified acronym of RWM) for variables.

Table 1.

Harvard Architecture

In reference to Figure 2, the Harvard architecture uses physically separate memories: program memory (PM) to store instructions and data memory (DM) to allocate variables. This requires dedicated address and data buses for each of them. As a result, the CPU is able to fetch instructions from program memory and operate on variables from data memory simultaneously.

Figure 2.

Harvard architecture block diagram

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