Delay Faults Testing

Delay Faults Testing

Marcel Baláž, Roland Dobai, Elena Gramatová
Copyright: © 2011 |Pages: 18
DOI: 10.4018/978-1-60960-212-3.ch017
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Abstract

Embedded digital blocks and their interconnections have to be verified by at-speed testing to satisfy the quality and reliability of nowadays System-on-Chips (SoCs). Once a chip is fabricated, it must be tested for pre-specified clock frequency and therefore testing has also to cover speed related faults as well as stuck-at faults. Claim for delay fault testing grows with new technologies. The importance of researching the delay fault testing grows rapidly and obviously the results are published separately for individual problems. The purpose of the chapter is to give an introduction to testing the timing malfunctions in digital circuits. The classification of existing basic and advanced delay fault models is presented with advantages and limitations. The latest test application techniques are described for scan-based synchronous and asynchronous circuits.
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Delay Faults Testing Background

Defects related to delays can be characterized as soft defects (sometimes referred to as dynamic defects or speed defects) and are modeled by delay faults. A circuit is said to have a delay fault if its output fails to reach the right value within the pre-specified timing constraints. The synchronous digital systems operation is usually synchronized by clock signals and it is necessary that all combinational logic elements attain steady state within the specified clock period. Delay faults in asynchronous circuits are specifically defined and tested. Delayed propagation in a digital circuit can be interpreted as:

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    an added propagation delay where the logic transition happens later,

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    an edge rate degradation where rise or fall time takes longer than expected.

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