Design Methodologies and Mapping Algorithms for Reconfigurable NoC-Based Systems

Design Methodologies and Mapping Algorithms for Reconfigurable NoC-Based Systems

Vincenzo Rana (Politecnico di Milano, Italy), Marco D. Santambrogio (Politecnico di Milano, Italy) and Alessandro Meroni (Politecnico di Milano, Italy)
DOI: 10.4018/978-1-61520-807-4.ch005
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Abstract

This chapter describes in details the different approaches and design methodologies that can be employed in order to create reconfigurable Network-on-Chip-based systems. The target architecture can be mainly defined either as a homogeneous or as a non-homogeneous grid of tiles. Furthermore, in addition to these architectures, it is also possible to identify a regular non-homogeneous solution, which is a sort of mix of the previous two. A second distinction can be done based on the reconfiguration capabilities that the target system can support. In particular, by using one of the previously introduced architectures, it is possible to develop a reconfigurable system, based on the NoC paradigm, in which the communication infrastructure, the mapping of the computational cores or both can be dynamically configured at run-time.
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Introduction

Nowadays, most of the reconfigurable embedded systems are designed for Field Programmable Gate Arrays (FPGAs) devices. An FPGA is an integrated circuit that can be programmed after it has been manufactured. FPGAs are similar in principle to, but have a vastly wider potential application than, programmable read-only memory (PROM) chips. FPGAs are used by engineers in the design of specialized ICs that can later be produced hard-wired in large quantities for distribution to computer manufacturers and end users. In addition to this, FPGAs can also be used to create systems which hardware configuration can be dynamically changed while they are up and running.

The first step that is necessary to perform, in order to create an FPGA-based reconfigurable embedded system, is the partitioning of the physical device in a set of disjoint regions. The shape and the distribution of these regions over the physical device represent the underlying reconfigurable architecture on which the system can be developed. The first part of this chapter will be devoted to the analysis of the different choices that can be made in order to create an optimal reconfigurable architecture for NoC-based embedded systems.

Once the underlying architecture has been defined, it is necessary to further split, as described in the second part of this chapter, the set of regions into two subsets: static regions and reconfigurable regions. In this way it is possible to define the components of the final system that will be considered as static and the ones that will be considered as reconfigurable. At run-time, in fact, it will be possible to modify the content of each reconfigurable region, while the static ones will remain fixed for the whole life of the system. This choice will deeply influence both the flexibility and the performance of the final system, in addition to the complexity of the design. A first design solution consists in configuring at run-time only the elements of the network (the switches and their interconnections), while maintaining fixed the location of the computational cores. A second solution is the choice to dynamically change at run-time the mapping of the computational cores on the communication infrastructure, which is considered as fixed. These two opposite solution can also be combined together in order to obtain a very high level of flexibility and adaptability, even if it considerably increases the time required to finalize the design of the system, its complexity and the run-time reconfigurations management task.

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